SLVSEW2A September   2020  – August 2021 TPS54618C-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation and Output Current
      3. 7.3.3  Bootstrap Voltage (Boot) and Low Dropout Operation
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Soft-Start Pin
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 7.3.11 Overcurrent Protection
      12. 7.3.12 Frequency Shift
      13. 7.3.13 Reverse Overcurrent Protection
      14. 7.3.14 Synchronize Using the RT/CLK Pin
      15. 7.3.15 Power Good (PWRGD Pin)
      16. 7.3.16 Overvoltage Transient Protection
      17. 7.3.17 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Simple Small Signal Model for Peak Current Mode Control
      2. 7.4.2 Small Signal Model for Frequency Compensation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Step One: Select the Switching Frequency
        2. 8.2.2.2 Step Two: Select the Output Inductor
        3. 8.2.2.3 Step Three: Choose the Output Capacitor
        4. 8.2.2.4 Step Four: Select the Input Capacitor
        5. 8.2.2.5 Step Five: Choose the Soft-Start Capacitor
        6. 8.2.2.6 Step Six: Select the Bootstrap Capacitor
        7. 8.2.2.7 Step Eight: Select Output Voltage and Feedback Resistors
          1. 8.2.2.7.1 Output Voltage Limitations
        8. 8.2.2.8 Step Nine: Select Loop Compensation Components
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Estimate
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Developmental Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Simple Small Signal Model for Peak Current Mode Control

Figure 7-11 shows an equivalent model for the TPS54618C-Q1 control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm of 245 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor R0 and capacitor Co model the open loop gain and frequency response of the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting a/c shows the small signal response of the frequency compensation. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing the RL with a current source with the appropriate load step amplitude and step rate in a time domain analysis.

GUID-EEDAFC6E-17AF-4E9B-ABB5-50381215474E-low.gifFigure 7-11 Small Signal Model for Loop Response

Figure 7-11 is a simple, small-signal model that can be used to understand how to design the frequency compensation. The TPS54618C-Q1 power stage can be approximated to a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 11 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 7-11) is the power stage transconductance. The gm for the TPS54618C-Q1 is 25 A/V. The low frequency gain of the power stage frequency response is the product of the transconductance and the load resistance as shown in Equation 12. As the load current increases and decreases, the low frequency gain decreases and increases, respectively. This variation with load can seem problematic at first glance, but the dominant pole moves with load current. The combined effect is highlighted by the dashed line in the right half of Figure 7-13. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation.

GUID-12A2EE23-86C0-4F62-929E-3927A8C7A4DF-low.gifFigure 7-12 Small Signal Model for Peak Current Mode Control
GUID-4A894331-69BF-4B52-92D2-0ADB94EBDBFA-low.gifFigure 7-13 Frequency Response Model for Peak Current Mode Control
Equation 11. GUID-2EF9B239-BE69-43AD-8A9E-BDB2B620030E-low.gif
Equation 12. GUID-6E147067-B336-4FCE-BFA7-CE109C92E5CF-low.gif
Equation 13. GUID-E57406AD-35CC-49B6-8A3B-A6B96FA23DEC-low.gif

Equation 14. GUID-8AC26492-FB79-42DA-BE02-E4699F940634-low.gif