SLVSFN6 December   2020 TPS54622-EP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency PWM Control
      2. 7.3.2  Continuous Current Mode Operation (CCM)
      3. 7.3.3  VIN and Power VIN Pins (VIN and PVIN)
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Adjusting the Output Voltage
      6. 7.3.6  Safe Start-Up Into Prebiased Outputs
      7. 7.3.7  Error Amplifier
      8. 7.3.8  Slope Compensation
      9. 7.3.9  Enable and Adjusting Undervoltage Lockout
      10. 7.3.10 Adjustable Switching Frequency and Synchronization (RT/CLK)
      11. 7.3.11 Slow Start (SS/TR)
      12. 7.3.12 Power Good (PWRGD)
      13. 7.3.13 Output Overvoltage Protection (OVP)
      14. 7.3.14 Overcurrent Protection
        1. 7.3.14.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.14.2 Low-Side MOSFET Overcurrent Protection
      15. 7.3.15 Thermal Shutdown
      16. 7.3.16 Small Signal Model for Loop Response
      17. 7.3.17 Simple Small Signal Model for Peak Current Mode Control
      18. 7.3.18 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Adjustable Switching Frequency (RT Mode)
      2. 7.4.2 Synchronization (CLK Mode)
      3. 7.4.3 Bootstrap Voltage (BOOT) and Low Dropout Operation
      4. 7.4.4 Sequencing (SS/TR)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedures
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Operating Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Slow-Start Capacitor Selection
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Undervoltage Lockout Setpoint
        9. 8.2.2.9  Output Voltage Feedback Resistor Selection
          1. 8.2.2.9.1 Minimum Output Voltage
        10. 8.2.2.10 Compensation Component Selection
        11. 8.2.2.11 Fast Transient Considerations
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Estimated Circuit Area
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
      2. 11.1.2 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.10 Compensation Component Selection

There are several industry techniques used to compensate DC-DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin from 60 to 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54622-EP. Since the slope compensation is ignored, the actual crossover frequency is usually lower than the crossover frequency used in the calculations.

First, the modulator pole, fpmod, and the ESR zero, fzmod, must be calculated using Equation 31 and Equation 32. For Cout, use a derated value of 75 µF. Use Equation 33 and Equation 34 to estimate a starting point for the closed loop crossover frequency, fco. Then the required compensation components may be derived. For this design example, fpmod is 3.86 kHz and fzmod is 707.4 kHz. Equation 33 is the geometric mean of the modulator pole and the ESR zero and Equation 34 is the geometric mean of the modulator pole and one half the switching frequency. Use a frequency near the lower of these two values as the intended crossover frequency, fco. In this case Equation 33 yields 52.2 kHz and Equation 34 yields 30.4 kHz. The lower value is 30.4 kHz. A slightly higher frequency of 30 kHz is chosen as the intended crossover frequency.

Equation 31. GUID-15CFFEE3-270C-41BC-A87B-7A4D75EFC18B-low.gif
Equation 32. GUID-24E73FB2-62F5-473A-B96B-8839C1706D4F-low.gif
Equation 33. GUID-D5B3397A-8954-4C1B-80BA-550C490E7DC7-low.gif
Equation 34. GUID-403044F3-279D-411D-BB77-4834ED715FA3-low.gif

Now the compensation components can be calculated. First calculate the value for R2 which sets the gain of the compensated network at the crossover frequency. Use Equation 35 to determine the value of R2.

Equation 35. GUID-797E141E-E644-4B47-885B-C5D6CA3D2A60-low.gif

Next calculate the value of C3. Together with R2, C3 places a compensation zero at the modulator pole frequency. Equation 36 to determine the value of C3.

Equation 36. GUID-9FC81796-2EED-4A4D-8C36-1802BF599295-low.gif

Using Equation 35 and Equation 36 the standard values for R4 and C4 are 3.74 kΩ and 0.01 µF.

An additional high-frequency pole can be used if necessary by adding a capacitor in parallel with the series combination of R4 and C4. The pole frequency can be placed at the ESR zero frequency of the output capacitor as given by Equation 8. Use Equation 37 to calculate the required capacitor value for C5.

Equation 37. GUID-9B611D84-D07C-4CA5-8907-8A006F026FF3-low.gif