SLVSB09C September   2011  – October 2017 TPS54623

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Safe Start-up into Pre-Biased Outputs
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Slope Compensation
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Slow Start (SS/TR)
      9. 7.3.9  Power Good (PWRGD)
      10. 7.3.10 Bootstrap Voltage (BOOT) and Low Dropout Operation
      11. 7.3.11 Sequencing (SS/TR)
      12. 7.3.12 Output Overvoltage Protection (OVP)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 High-side MOSFET Overcurrent Protection
        2. 7.3.13.2 Low-side MOSFET Overcurrent Protection
      14. 7.3.14 Thermal Shutdown
      15. 7.3.15 Small Signal Model for Loop Response
      16. 7.3.16 Simple Small Signal Model for Peak Current Mode Control
      17. 7.3.17 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fixed Frequency PWM Control
      2. 7.4.2 Continuous Current Mode Operation (CCM)
      3. 7.4.3 Light Load Efficiency Operation
      4. 7.4.4 Adjustable Switching Frequency and Synchronization (RT/CLK)
        1. 7.4.4.1 Adjustable Switching Frequency (RT Mode)
        2. 7.4.4.2 Synchronization (CLK mode)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Fast Transient Considerations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Operating Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Slow Start Capacitor Selection
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Under Voltage Lockout Set Point
        9. 8.2.2.9  Output Voltage Feedback Resistor Selection
          1. 8.2.2.9.1 Minimum Output Voltage
        10. 8.2.2.10 Compensation Component Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Estimated Circuit Area
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
      3. 11.1.3 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage VIN –0.3 20 V
PVIN –0.3 20
EN –0.3 6
BOOT –0.3 27
VSENSE –0.3 3
COMP –0.3 3
PWRGD –0.3 6
SS/TR –0.3 3
RT/CLK –0.3 6
Output voltage BOOT-PH 0 7.5 V
PH –1 20
PH (10-ns transient) –3 20
Vdiff (GND to exposed thermal pad) –0.2 0.2 V
Source current RT/CLK ±100 µA
PH Current limit A
Sink current PH Current limit A
PVIN Current limit A
COMP ±200 µA
PWRGD –0.1 5 mA
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VVIN Input voltage 4.5 17 V
VPVIN Input voltage 1.7 17 V
IOUT Output current 0 6 A
TJ Operating junction temperature –40 150 °C

6.4 Thermal Information

THERMAL METRIC(1)(2) TPS54623 UNIT
RHL (VQFN)
14 PINS
RθJA Junction-to-ambient Thermal resistance 40.1 °C/W
Test board(3) 32
RθJC(top) Junction-to-case (top) thermal resistance 34.4 °C/W
RθJB Junction-to-board thermal resistance 11.4 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 11.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below 150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more information.
(3) Test board conditions:
  1. 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch
  2. 2 oz. copper traces located on the top of the PCB
  3. 2 oz. copper ground planes on the 2 internal layers and bottom layer
  4. 4 0.010 inch thermal vias located under the device package

6.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 4.5 V to 17 V, PVIN = 1.6 V to 17 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN AND PVIN PINS)
PVIN operating input voltage 1.6 17 V
VIN operating input voltage 4.5 17 V
VIN internal UVLO threshold VIN rising 4.0 4.5 V
VIN internal UVLO hysteresis 150 mV
VIN shutdown supply Current EN = 0 V 2 5 μA
VIN operating – non switching supply current VSENSE = 810 mV 250 500 μA
ENABLE AND UVLO (EN PIN)
Enable threshold Rising 1.21 1.26 V
Enable threshold Falling 1.10 1.17 V
Input current EN = 1.1 V 1.15 μA
Hysteresis current EN = 1.3 V 3.3 μA
VOLTAGE REFERENCE
Voltage reference 0 A ≤ IOUT ≤ 6 A 0.594 0.6 0.606 V
MOSFET
High-side switch resistance BOOT-PH = 3 V 32 60 mΩ
High-side switch resistance(1) BOOT-PH = 6 V 26 40 mΩ
Low-side switch resistance(1) VIN = 12 V 19 30 mΩ
ERROR AMPLIFIER
Error amplifier Transconductance (gm) –2 μA < ICOMP < 2 μA, V(COMP) = 1 V 1300 μMhos
Error amplifier dc gain VSENSE = 0.6 V 1000 3100 V/V
Error amplifier source/sink V(COMP) = 1 V, 100 mV input overdrive ±110 μA
Start switching peak current threshold 1 A
COMP to Iswitch gm 16 A/V
CURRENT LIMIT
High-side switch current limit threshold 8 11 14 A
Low-side switch sourcing current limit 6.5 10 15 A
Low-side switch sinking current limit 200 600 mA
Hiccup wait time 512 Cycles
Hiccup time before re-start 16384 Cycles
THERMAL SHUTDOWN
Thermal shutdown 160 175 °C
Thermal shutdown hysteresis 10 °C
Thermal shutdown hiccup time 16384 Cycles
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Minimum switching frequency RRT = 240 kΩ (1%) 160 200 240 kHz
Switching frequency RRT = 100 kΩ (1%) 400 480 560 kHz
Maximum switching frequency RRT = 29 kΩ (1%) 1440 1600 1760 kHz
Minimum pulse width 20 ns
RT/CLK high threshold 2 V
RT/CLK low threshold 0.8 V
RT/CLK falling edge to PH rising edge delay Measure at 500 kHz with RT resistor in series 66 ns
Switching frequency range (RT mode set point and PLL mode) 200 1600 kHz
PH (PH PIN)
Minimum on-time Measured at 90% to 90% of VIN, 25°C, IPH = 2 A 94 145 ns
Minimum off-time BOOT-PH ≥ 3 V 0 ns
BOOT (BOOT PIN)
BOOT-PH UVLO 2.1 3 V
SLOW START AND TRACKING (SS/TR PIN)
SS charge current 2.3 μA
SS/TR to VSENSE matching V(SS/TR) = 0.4 V 20 60 mV
POWER GOOD (PWRGD PIN)
VSENSE threshold VSENSE falling (Fault) 92% Vref
VSENSE rising (good) 94% Vref
VSENSE rising (Fault) 106% Vref
VSENSE falling (Good) 104% Vref
Output high leakage VSENSE = Vref, V(PWRGD) = 5.5 V 30 100 nA
Output low I(PWRGD) = 2 mA 0.3 V
Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 μA 0.6 1 V
Minimum SS/TR voltage for PWRGD 1.4 V
(1) Measured at pins

6.6 Typical Characteristics

TPS54623 rdson_tj_lvs949.gif Figure 1. High-Side RDS(on) vs Temperature
TPS54623 vref_junc_lvsa70.gif Figure 3. Voltage Reference vs Temperature
TPS54623 isd_vi_lvs949.gif Figure 5. Shutdown Quiescent Current
vs Input Voltage
TPS54623 hys_pullup_lvs949.gif Figure 7. Pin Pullup Current vs Temperature
TPS54623 iq_vi_lvsb09.gif Figure 9. Non-Switching Operating Quiescent
Current (VIN) vs Input Voltage
TPS54623 sstr_junc_lvsa70.gif Figure 11. (SS/TR - VSENSE) Offset vs Temperature
TPS54623 hi_sd_cur_vi_lvs949.gif Figure 13. High-Side Current limit Threshold
vs Input Voltage
TPS54623 mincon_duty_lvsa70.gif Figure 15. Minimum Controllable Duty Ratio
vs Junction Temperature
TPS54623 rdsonl_tj_lvs949.gif Figure 2. Low-Side RDS(on) vs Temperature
TPS54623 fsw_tj_lvsa70.gif Figure 4. Oscillator Frequency vs Temperature
TPS54623 hys_tj_lvs949.gif Figure 6. EN Pin Hysteresis Current vs Temperature
TPS54623 en_tj_lvs949.gif Figure 8. Pin UVLO Threshold vs Temperature
TPS54623 ss_tj_lvs949.gif Figure 10. Slow Start Charge Current
vs Temperature
TPS54623 pwrgd_junc_lvsa70.gif Figure 12. PWRGD Threshold vs Temperature
TPS54623 t_tj_lvsa70.gif Figure 14. Minimum Controllable On Time
vs Temperature
TPS54623 boot_tj_lvs949.gif Figure 16. BOOT-PH UVLO Threshold
vs Temperature