SLVSC33A August   2013  – October 2022 TPS54625

PRODUCTION DATA  

  1. FEATURES
  2. APPLICATIONS
  3. DESCRIPTION
  4. ORDERING INFORMATION (1)
  5. ABSOLUTE MAXIMUM RATINGS
  6. THERMAL INFORMATION
  7. RECOMMENDED OPERATING CONDITIONS
  8. ELECTRICAL CHARACTERISTICS
  9. DEVICE INFORMATION
  10. 10OVERVIEW
  11. 11DETAILED DESCRIPTION
    1. 11.1 PWM Operation
    2. 11.2 PWM Frequency and Adaptive On-Time Control
    3. 11.3 Soft Start and Pre-Biased Soft Start
    4. 11.4 Power Good
    5. 11.5 Output Discharge Control
    6. 11.6 Current Protection
    7. 11.7 Over/Under Voltage Protection
    8. 11.8 UVLO Protection
    9. 11.9 Thermal Shutdown
  12. 12TYPICAL CHARACTERISTICS
  13. 13DESIGN GUIDE
    1. 13.1 Step By Step Design Procedure
    2. 13.2 Output Voltage Resistors Selection
    3. 13.3 Output Filter Selection
    4. 13.4 Input Capacitor Selection
    5. 13.5 Bootstrap Capacitor Selection
    6. 13.6 VREG5 Capacitor Selection
  14. 14THERMAL INFORMATION
  15. 15LAYOUT CONSIDERATIONS
  16. 16Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Soft Start and Pre-Biased Soft Start

The soft start function is adjustable. When the EN pin becomes high, 6-μA current begins charging the capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is 6 μA.

Equation 1. GUID-05924323-D0A8-4A32-97CD-A777A4FA29D0-low.gif

TPS54625 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft-start becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation .