SLVSC33A August   2013  – October 2022 TPS54625

PRODUCTION DATA  

  1. 1 FEATURES
  2. 2 APPLICATIONS
  3. 3 DESCRIPTION
  4. 4 ORDERING INFORMATION (1)
  5. 5 ABSOLUTE MAXIMUM RATINGS
  6. 6 THERMAL INFORMATION
  7. 7 RECOMMENDED OPERATING CONDITIONS
  8. 8 ELECTRICAL CHARACTERISTICS
  9. 9 DEVICE INFORMATION
  10. 10OVERVIEW
  11. 11DETAILED DESCRIPTION
    1. 11.1 PWM Operation
    2. 11.2 PWM Frequency and Adaptive On-Time Control
    3. 11.3 Soft Start and Pre-Biased Soft Start
    4. 11.4 Power Good
    5. 11.5 Output Discharge Control
    6. 11.6 Current Protection
    7. 11.7 Over/Under Voltage Protection
    8. 11.8 UVLO Protection
    9. 11.9 Thermal Shutdown
  12. 12TYPICAL CHARACTERISTICS
  13. 13DESIGN GUIDE
    1. 13.1 Step By Step Design Procedure
    2. 13.2 Output Voltage Resistors Selection
    3. 13.3 Output Filter Selection
    4. 13.4 Input Capacitor Selection
    5. 13.5 Bootstrap Capacitor Selection
    6. 13.6 VREG5 Capacitor Selection
  14. 14THERMAL INFORMATION
  15. 15LAYOUT CONSIDERATIONS
  16. 16Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 DEVICE INFORMATION

GUID-B85A57FF-56FC-42C8-9AC0-D9790407809C-low.gif
Pin Functions
PIN DESCRIPTION
NAME NUMBER
VO 1 Connect to output of converter. This pin is used for output discharge function.
VFB 2 Converter feedback input. Connect with feedback resistor divider.
VREG5 3 5.5V power supply output. An external capacitor (typical 1uF) should be connected to GND. VREG5 is not active when EN is low.
SS 4 Soft start control. An external capacitor should be connected to GND.
GND 5 Signal ground pin.
PG 6 Open drain power good output
EN 7 Enable control input. EN is active high and must be pulled up to enable the device.
PGND1, PGND2 8, 9 Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND and GND strongly together near the IC.
SW1,SW2 10, 11 Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current comparator.
VBST 12 Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 and VBST pin.
VIN1, VIN2 13, 14 Power Input and connected to high side NFET drain. Supply Input for 5V internal linear regulator for the control circuitry
PowerPAD™ Back side Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected to PGND
GUID-28A8FA51-7AF1-4A85-A910-5461CBD5C098-low.gif Figure 9-1 FUNCTIONAL BLOCK DIAGRAM (HTSSOP)