SLVSBF3B June   2012  – May 2019 TPS54678

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Output Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation and Output Current
      3. 7.3.3  Bootstrap Voltage (Boot) and Low Dropout Operation
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Soft-Start Pin
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 7.3.11 Overcurrent Protection
        1. 7.3.11.1 High-Side Overcurrent Protection
        2. 7.3.11.2 Low-Side Overcurrent Protection
      12. 7.3.12 Safe Start-Up into Prebiased Outputs
      13. 7.3.13 Synchronize Using the RT/CLK Pin
      14. 7.3.14 Power Good (PWRGD Pin)
      15. 7.3.15 Overvoltage Transient Protection
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Small Signal Model for Loop Response
      2. 7.4.2 Simple Small Signal Model for Peak Current Mode Control
      3. 7.4.3 Small Signal Model for Frequency Compensation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Step One: Select the Switching Frequency
        3. 8.2.2.3 Step Two: Select the Output Inductor
        4. 8.2.2.4 Step Three: Choose the Output Capacitor
        5. 8.2.2.5 Step Four: Select the Input Capacitor
        6. 8.2.2.6 Step Five: Choose the Soft-Start Capacitor
        7. 8.2.2.7 Step Six: Select the Bootstrap Capacitor
        8. 8.2.2.8 Step Eight: Select Output Voltage and Feedback Resistors
          1. 8.2.2.8.1 Output Voltage Limitations
        9. 8.2.2.9 Step Nine: Select Loop Compensation Components
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Additional Information About Application Curves
          1. 8.2.3.1.1 Efficiency
          2. 8.2.3.1.2 Voltage Ripple Measurements
          3. 8.2.3.1.3 Start-Up and Shutdown Waveforms
          4. 8.2.3.1.4 Hiccup Mode Current Limit
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Estimate
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.3 Small Signal Model for Frequency Compensation

The TPS54678 uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits. The compensation circuits are shown in Figure 29. The Type 2 circuits are normally implemented in high-bandwidth power supply designs using low ESR output capacitors. In Type 2A, one additional high-frequency pole is added to attenuate high-frequency noise.

TPS54678 ai_freq_comp_sds.gifFigure 29. Types of Frequency Compensation

The design guidelines for TPS54678 loop compensation are as follows:

  1. Set up crossover frequency fc.
  2. R3 can be determined by Equation 10:
    3. Equation 10. TPS54678 eq10_lvsbf3.gif

    where

    • gmea is the GM amplifier gain,
    • gmPS is the power stage gain (20 A/V).
  3. Place a compensation zero at the dominant pole TPS54678 eq8_lvsbf3.gif C1 can be determined by Equation 11:
    4. Equation 11. TPS54678 eq11_lvsbf3.gif
  4. C2 is optional. It can be used to cancel the zero from ESR of the Co in Equation 12:
    5. Equation 12. TPS54678 eq12_lvsbf3.gif