8.2.2.4 Step Three: Choose the Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. Along with the inductor, the output capacitor determines the output voltage ripple, and also how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these two criteria.

The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not due to limited control speed. The regulator is temporarily not able to supply sufficient change in output current if there is a large, fast increase or decrease in the current needs of the load such as transitioning from no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change, or conversely, absorb the excess current from the inductor. Because the output voltage is less than half the input voltage, the worst-case deviation in output voltage occurs when the load has an extremely rapid reduction in current, or a load dump. The desired specification is a 50% or 3-A load step, and a resulting voltage deviation of no more than 5%, or 60mV. When a load dump occurs, the excess stored current in the inductor will tend to charge the output capacitors, and the best the converter can achieve to limit the increase in output voltage is to fold back the duty cycle to zero. Under these circumstances, the amount of rise in output voltage is defined by the energy from the choke being fully absorbed by the capacitor bank. Equation 18 through Equation 20 can be used to calculate the required capacitor bank value.

For this example, the transient load response is specified as a 5% change in Vout for a 50% load step from 3 A to 0 A. So, ΔI_OUT = 3 A and ΔV_OUT = 0.05 × 1.2 = 0.06 V. Using these numbers gives a minimum capacitance of 73.2 μF. This calculation does not take the ESR of the output capacitor into account in the output voltage change, and it does not account for latency in control loop speed. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.

Equation 18.

Equation 19.

Solving for C:

Equation 20.

This 73.17 µF defines the minimum capacitance required to meet the transient spec; however, because the control loop speed is finite, more capacitance than this is required to meet desired performance.

Equation 21 calculates the minimum output capacitance needed to meet the output voltage ripple specification. In this case, the maximum output voltage ripple is 60 mV. Under this requirement, Equation 21 yields 13.33 µF.

Equation 21.

where

• F_SW is the switching frequency,
• V_RIPPLE is the maximum allowable output voltage ripple,
• and Iripple is the inductor ripple current.

Equation 22 calculates the maximum ESR for the capacitor bank to meet the output voltage ripple specification. Equation 22 indicates the ESR should be less than 37.5 mΩ. In this case, the ESR of the ceramic capacitor bank is less than 37.5 mΩ.

Equation 22.

Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases the minimum value calculated in Equation 20. For this example, five 47-μF 10-V X5R ceramic capacitors with 3 mΩ of ESR are used. The estimated capacitance after derating is 5 × 47 μF × 0.9 = 211.5 μF.