SLUSF28 Data sheet

SLUSF28 November 2023 TPS546A24S

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RVF|40
- MPQF268C

Thermal pad, mechanical data (Package|Pins)

RVF|40
- QFND333E

Orderable Information

7.2.2.10 Compensation Selection (MSEL1 Pin)

The resistor to AGND for MSEL1 selects the (B1h) USER_DATA_01 (COMPENSATION_CONFIG) values to program the following voltage loop and current loop gains. For options other than the EEPROM code (MSEL1 shorted to AGND or MSEL1 to AGND resistor code 0), the current and voltage loop zero and pole frequencies are scaled with the programmed switching frequency.

Based on Current Error Integrator, calculate the mid-band current loop gain with Equation 24.

Equation 24.

Find the smaller value closest to 8.7 in Table 6-9 and this is .

To calculate the target voltage loop gain, first use Equation 25 to calculate the output impedance. Use Equation 26 to calculate the target voltage loop gain.

Equation 25.

Equation 26.

Find the smaller value closest to 4 in Table 6-9 for voltage loop gain and this is 4. This setting gives a stable design but through bench evaluation the voltage loop gain was reduced to 1 to improve the gain and phase margin with the reduced ILOOP gain. The calculated current and voltage loop gain correspond to compensation setting 17. To use this compensation setting resistor to AGND code 1 is needed. With this compensation code the even resistor divider code must be used to set the switching frequency. Divider code 9 sets the fsw to 650 kHz. Resistor to AGND code 1 and resistor divider code is selected using an MSEL1 resistor divider of R_TOP = 3.16 kΩ and R_BOT = 5.62 kΩ.

The procedure given is meant to give a stable design. Further optimization of the compensation is often possible through testing the design on the bench. Increasing the voltage loop gain increases the loop bandwidth to improve the transient response but make sure to verify there is still sufficient gain and phase margin. The maximum voltage loop bandwidth possible is limited by these stability margins. Decreasing the current loop gain can help to minimize pulse-width jitter but this typically comes with a tradeoff of decreased phase margin. Lastly, the pole and zero locations can also be adjusted through PMBus. For example, it can be beneficial to use the CPV capacitor in the voltage loop to add a pole at the same frequency of the ESR zero when using high ESR output capacitors.

When using a larger inductance, the current loop gain that can be selected through pin strapping can be much lower than the calculated target value. If this happens, the voltage loop gain must also be scaled back by about the same amount to keep sufficient phase margin. For higher voltage loop bandwidth, the inductance can be decreased to reduce the current loop gain needed or higher current loop gain can be programmed through the PMBus command USER_DATA_01 (COMPENSATION_CONFIG).