SLUSF28 November 2023 TPS546A24S
PRODUCTION DATA
The TPS546A24S devices have three internal linear regulators receiving power from AVIN and providing suitable bias (1.5 V, 1.8 V, and 5 V) for the internal circuitry of the device. External bypass pins for VDD5 and BP1V5 must be bypassed to their respective grounds for the converter to function properly. BP1V5 requires a minimum of 1 μF of capacitance connected to DRTN. VDD5 requires a minimum 4.7 μF of capacitance connected to PGND. After AVIN, 1.5-V, 1.8-V, and 5-V reach their respective UVLOs, the device initiates a power-on reset, after which the device can be communicated with through PMBus for configuration and users can store defaults to the NVM.
The VDD5 has internally fixed undervoltage lockout of 3.9 V (typical) to enable power-stage conversion. The VDD5 regulator can also be fed by external supply to reduce internal power dissipation and improve efficiency by eliminating the loss in the internal LDO, or to allow operation with AVIN less than 4 V. The external supply must be higher voltage than the LDO regulation voltage programmed by (B5h) USER_DATA_05 (POWER_STAGE_CONFIG).
Place bypass capacitors as close as possible to the device pins, with a minimum return loop back to their respective ground. Keep the return loop away from fast switching voltage and the main current path — see the layout for details. Poor bypassing can degrade the performance of the regulator.
The use of the internal regulators to power other circuits is not recommended because the loads placed on the regulators can adversely affect operation of the controller.