SLUSF28 November 2023 TPS546A24S
PRODUCTION DATA
CMD Address | 7Bh |
Write Transaction: | Write Byte |
Read Transaction: | Read Byte |
Format: | Unsigned Binary (1 byte) |
Phased: | Yes |
NVM Back-up: | No |
Updates: | On-the-fly |
The STATUS_IOUT command returns one data byte with contents as follows. All supported bits can be cleared either by CLEAR_FAULTS, or individually by writing 1b to the (7Bh) STATUS_IOUT register in their position, per the PMBus 1.3.1 Part II specification section 10.2.4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RW | R | RW | RW | R | R | R | R |
IOUT_OCF | 0 | IOUT_OCW | IOUT_UCF | 0 | 0 | 0 | 0 |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | Access | Reset | Description |
---|---|---|---|---|
7 | IOUT_ OCF | RW | 0b | 0b: Latched flag indicating IOUT OC fault has NOT occurred. 1b: Latched flag indicating IOUT OC fault has occurred. |
6 | Not Supported | R | 0b | Not supported and always set to 0b. |
5 | IOUT_ OCW | RW | 0b | 0b: Latched flag indicating IOUT OC warn has NOT occurred. 1b: Latched flag indicating IOUT OC warn has occurred. |
4 | IOUT_UCF | RW | 0b | 0b: Latched flag indicating IOUT UC fault has NOT occurred. 1b: Latched flag indicating IOUT UC fault has occurred. |
3:0 | Not Supported | R | 0000b | Not supported and always set to 0000b. |
All bits which can trigger SMBALERT have a corresponding bit in SMBALERT_MASK.