SLVSH95 July   2024 TPS546C25

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  D-CAP4 Control
        1. 6.3.1.1 Loop Compensation
      2. 6.3.2  Internal VCC LDO and Using an External Bias on VCC Pin and VDRV Pin
      3. 6.3.3  Input Undervoltage Lockout (UVLO)
        1. 6.3.3.1 Fixed VCC_OK UVLO
        2. 6.3.3.2 Fixed VDRV UVLO
        3. 6.3.3.3 Programmable PVIN UVLO
        4. 6.3.3.4 Control (CNTL)Enable
      4. 6.3.4  Differential Remote Sense and Internal, External Feedback Divider
      5. 6.3.5  Set the Output Voltage and VORST#
      6. 6.3.6  Start-Up and Shutdown
      7. 6.3.7  Dynamic Voltage Slew Rate
      8. 6.3.8  Set Switching Frequency
      9. 6.3.9  Switching Node (SW)
      10. 6.3.10 Overcurrent Limit and Low-side Current Sense
      11. 6.3.11 Negative Overcurrent Limit
      12. 6.3.12 Zero-Crossing Detection
      13. 6.3.13 Input Overvoltage Protection
      14. 6.3.14 Output Overvoltage and Undervoltage Protection
      15. 6.3.15 Overtemperature Protection
      16. 6.3.16 Telemetry
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 DCM Light Load Operation
      3. 6.4.3 Powering the Device From a 12V Bus
      4. 6.4.4 Powering the Device From a Split-rail Configuration
      5. 6.4.5 Pin Strapping
        1. 6.4.5.1 Programming MSEL1
        2. 6.4.5.2 Programming PMB_ADDR
        3. 6.4.5.3 Programming MSEL2
        4. 6.4.5.4 Programming VSEL\FB
    5. 6.5 Programming
      1. 6.5.1 Supported PMBus Commands
  8. Register Maps
    1. 7.1  Conventions for Documenting Block Commands
    2. 7.2  (01h) OPERATION
    3. 7.3  (02h) ON_OFF_CONFIG
    4. 7.4  (03h) CLEAR_FAULTS
    5. 7.5  (04h) PHASE
    6. 7.6  (09h) P2_PLUS_WRITE
    7. 7.7  (0Ah) P2_PLUS_READ
    8. 7.8  (0Eh) PASSKEY
    9. 7.9  (10h) WRITE_PROTECT
    10. 7.10 (15h) STORE_USER_ALL
    11. 7.11 (16h) RESTORE_USER_ALL
    12. 7.12 (19h) CAPABILITY
    13. 7.13 (1Bh) SMBALERT_MASK
    14. 7.14 (20h) VOUT_MODE
    15. 7.15 (21h) VOUT_COMMAND
    16. 7.16 (22h) VOUT_TRIM
    17. 7.17 (24h) VOUT_MAX
    18. 7.18 (25h) VOUT_MARGIN_HIGH
    19. 7.19 (26h) VOUT_MARGIN_LOW
    20. 7.20 (27h) VOUT_TRANSITION_RATE
    21. 7.21 (29h) VOUT_SCALE_LOOP
    22. 7.22 (2Ah) VOUT_SCALE_MONITOR
    23. 7.23 (2Bh) VOUT_MIN
    24. 7.24 (33h) FREQUENCY_SWITCH
    25. 7.25 (35h) VIN_ON
    26. 7.26 (36h) VIN_OFF
    27. 7.27 (39h) IOUT_CAL_OFFSET
    28. 7.28 (40h) VOUT_OV_FAULT_LIMIT
    29. 7.29 (41h) VOUT_OV_FAULT_RESPONSE
    30. 7.30 (42h) VOUT_OV_WARN_LIMIT
    31. 7.31 (43h) VOUT_UV_WARN_LIMIT
    32. 7.32 (44h) VOUT_UV_FAULT_LIMIT
    33. 7.33 (45h) VOUT_UV_FAULT_RESPONSE
    34. 7.34 (46h) IOUT_OC_FAULT_LIMIT
    35. 7.35 (48h) IOUT_OC_LV_FAULT_LIMIT
    36. 7.36 (49h) IOUT_OC_LV_FAULT_RESPONSE
    37. 7.37 (4Ah) IOUT_OC_WARN_LIMIT
    38. 7.38 (4Fh) OT_FAULT_LIMIT
    39. 7.39 (50h) OT_FAULT_RESPONSE
    40. 7.40 (51h) OT_WARN_LIMIT
    41. 7.41 (55h) VIN_OV_FAULT_LIMIT
    42. 7.42 (60h) TON_DELAY
    43. 7.43 (61h) TON_RISE
    44. 7.44 (64h) TOFF_DELAY
    45. 7.45 (65h) TOFF_FALL
    46. 7.46 (78h) STATUS_BYTE
    47. 7.47 (79h) STATUS_WORD
    48. 7.48 (7Ah) STATUS_VOUT
    49. 7.49 (7Bh) STATUS_IOUT
    50. 7.50 (7Ch) STATUS_INPUT
    51. 7.51 (7Dh) STATUS_TEMPERATURE
    52. 7.52 (7Eh) STATUS_CML
    53. 7.53 (7Fh) STATUS_OTHER
    54. 7.54 (80h) STATUS_MFR_SPECIFIC
    55. 7.55 (88h) READ_VIN
    56. 7.56 (8Bh) READ_VOUT
    57. 7.57 (8Ch) READ_IOUT
    58. 7.58 (8Dh) READ_TEMPERATURE_1
    59. 7.59 (98h) PMBUS_REVISION
    60. 7.60 (99h) MFR_ID
    61. 7.61 (9Ah) MFR_MODEL
    62. 7.62 (9Bh) MFR_REVISION
    63. 7.63 (ADh) IC_DEVICE_ID
    64. 7.64 (AEh) IC_DEVICE_REV
    65. 7.65 (D1h) SYS_CFG_USER1
    66. 7.66 (D2h) PMBUS_ADDR
    67. 7.67 (D4h) COMP
    68. 7.68 (D5h) VBOOT_OFFSET_1
    69. 7.69 (D6h) STACK_CONFIG
    70. 7.70 (D8h) PIN_DETECT_OVERRIDE
    71. 7.71 (D9h) NVM_CHECKSUM
    72. 7.72 (DAh) READ_TELEMETRY
    73. 7.73 (79h) STATUS_ALL
    74. 7.74 (DDh) EXT_WRITE_PROTECTION
    75. 7.75 (A4h) IMON_CAL
    76. 7.76 (FCh) FUSION_ID0
    77. 7.77 (FDh) FUSION_ID1
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Input Capacitor Selection
        2. 8.2.3.2 Inductor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 Compensation Selection
        5. 8.2.3.5 VCC and VRDV Bypass Capacitors
        6. 8.2.3.6 BOOT Capacitor Selection
        7. 8.2.3.7 VOSNS and GOSNS Capacitor Selection
        8. 8.2.3.8 PMBus Address Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on TPS546C25EVM
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • VBD|33
Thermal pad, mechanical data (Package|Pins)
Orderable Information

(46h) IOUT_OC_FAULT_LIMIT

CMD Address 46h
Write Transaction: Write Word
Read Transaction: Read Word
Format: LINEAR11
Phased: Yes
NVM Backup: EEPROM or Pin Detection
Updates: On-the-fly

The IOUT_OC_FAULT_LIMIT command sets the value of the output current that causes the overcurrent detector to indicate an overcurrent fault condition. The thresholds selected here are compared to the sensed low-side valley current. See Overcurrent Limit and Low-side Current Sense for more details.

Return to Supported PMBus Commands.

Figure 7-41 (46h) IOUT_OC_FAULT_LIMIT Register Map
15 14 13 12 11 10 9 8
R R R R R R R R
EXPONENT IOUT_OC_FAULT_LIMIT
7 6 5 4 3 2 1 0
R* or R/W** R* or R/W** R/W R/W R/W R/W R/W R/W
IOUT_OC_FAULT_LIMIT
LEGEND: R/W = Read/Write; R = Read only
Table 7-39 Register Field Descriptions
Bit Field Access Reset Description
15:11 EXPONENT R 00000b Linear format two’s complement exponent. The exponent is configured automatically through other settings, with a result of

1b: 0.5A LSB

0b: 1A LSB

10:8 Reserved R 00000b Not used and always set to 0.
7 IOUT_OC_FAULT_LIMIT R* or R/W** 0b

* When STACK_NUMBER[1:0] = 1b, bit 7 is read only.

** When STACK_NUMBER[1:0] is >2b, bit 7 is readable and writeable as described in P2_PLUS_WRITE Commands and Response to P2_PLUS_READ Commands descriptions.

6 IOUT_OC_FAULT_LIMIT R* or R/W*** 0b

* When STACK_NUMBER[1:0] = 1b, bit 6 is read only.

** When STACK_NUMBER[1:0] is >1b, bit 6 is readable and writeable as described in P2_PLUS_WRITE Commands and Response to P2_PLUS_READ Commands descriptions.

5:0 IOUT_OC_FAULT_LIMIT R/W NVM These bits select the IOUT valley current limiting threshold.

Data Validity

Every mantissa binary value in the writable bits is writeable and readable. However, the actual divider is set to the nearest supported value. Additionally, that mantissa value restored from EEPROM is fixed for each setting supported in hardware.

* Attempts to change the read-only bits (IOUT_OC_FAULT_LIMIT[15:8]) will be considered invalid/unsupported data when STACK_NUMBER[1:0] is = 1b. The device will NACK the unsupported data and the received value will be ignored. The ’cml’ bit in the STATUS_BYTE and the ‘ivd’ bit in the STATUS_CML registers will be set.

** Attempts to change the read-write bit (IOUT_OC_FAULT_LIMIT[7]) will only be considered valid data if STACK_NUMBER[1:0] is > 2b.

*** Attempts to change the read-write bit (IOUT_OC_FAULT_LIMIT[6]) will only be considered valid data if STACK_NUMBER[1:0] is > 1b.

Table 7-40 IOUT_OC_FAULT_LIMIT supported values and EEPROM restore values
IOUT_OC_FAULT_LIMIT [5:0] IOUT_OC (A)
Greater than or equal to Less than
11d 10
11d 14d 12
14d 17d 15
17d 20d 19
20d 23d 21 (60%)
23d 26d 24
26d 29d 28 (80%)
29d 31d 30
31d 34d 32
34d 37d 35 (100%)
37d 40d 39
40d 40

Response to P2_PLUS_WRITE Commands

When the PMBus host attempts to execute a P2+ write to IOUT_OC_FAULT_LIMIT with the PHASE data in the command set to FFh, the expectation is to equally divide the commanded net “Stack OC” level among the phases as their individual “Phase OC” settings. In order to achieve that, the device does the following:

  • If STACK_NUMBER[1:0] is 2 (i.e., 2-phase operation), then the incoming commanded Stack OC level is converted to the individual Phase OC level by adding 1, followed by right-shift of 1 bit (i.e., dividing by 2, rounded up). The resulting Phase OC level is then binned into the appropriate IOUT_OC value based on the IOUT__OC_FAULT_LIMIT tables above.
  • If STACK_NUMBER[1:0] is 4 (i.e., 4-phase operation), then the incoming commanded Stack OC level is converted to the individual Phase OC level by adding 2, followed by right-shift of 2 bits (i.e., dividing by 4, rounded up). The resulting Phase OC level is then binned into the appropriate IOUT_OC value based on the IOUT_OC_FAULT_LIMIT tables above.
  • If STACK_NUMBER[1:0] is 3 (i.e., 3-phase operation), then the incoming commanded Stack OC level is directly converted to the PHASE IOUT_OC value using the table below:

Table 7-41 3-ph STACK OC IOUT_OC_FAULT_LIMIT supported values and EEPROM restore values
3-ph STACK OC commanded[5:0] PHASE IOUT_OC (A)
Greater than or equal to Less than
33d 10
33d 41d 12
41d 51d 15
51d 60d 19
60d 68d 21 (60%)
68d 78d 24
78d 87d 28 (80%)
87d 93d 30
93d 101d 32
101d 111d 35 (100%)
111d 119d 39
119d 40

Response to P2_PLUS_READ Commands

When the PMBus host attempts to execute a P2+ read on IOUT_OC_FAULT_LIMIT with the PHASE data in the command set to FFh, only the primary device will respond to P2+ read commands with incoming data for PHASE=FFh. The primary device multiplies the IOUT_OC level by the STACK_NUMBER and reports the product back on the PMBus. For example, if the IOUT_OC is 24A for the primary phase in a 3-phase rail, then a P2+ read with PHASE=FFh will yield 24 x 3 = 72A as the read-back value.