SLVSH95 July   2024 TPS546C25

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  D-CAP4 Control
        1. 6.3.1.1 Loop Compensation
      2. 6.3.2  Internal VCC LDO and Using an External Bias on VCC Pin and VDRV Pin
      3. 6.3.3  Input Undervoltage Lockout (UVLO)
        1. 6.3.3.1 Fixed VCC_OK UVLO
        2. 6.3.3.2 Fixed VDRV UVLO
        3. 6.3.3.3 Programmable PVIN UVLO
        4. 6.3.3.4 Control (CNTL)Enable
      4. 6.3.4  Differential Remote Sense and Internal, External Feedback Divider
      5. 6.3.5  Set the Output Voltage and VORST#
      6. 6.3.6  Start-Up and Shutdown
      7. 6.3.7  Dynamic Voltage Slew Rate
      8. 6.3.8  Set Switching Frequency
      9. 6.3.9  Switching Node (SW)
      10. 6.3.10 Overcurrent Limit and Low-side Current Sense
      11. 6.3.11 Negative Overcurrent Limit
      12. 6.3.12 Zero-Crossing Detection
      13. 6.3.13 Input Overvoltage Protection
      14. 6.3.14 Output Overvoltage and Undervoltage Protection
      15. 6.3.15 Overtemperature Protection
      16. 6.3.16 Telemetry
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 DCM Light Load Operation
      3. 6.4.3 Powering the Device From a 12V Bus
      4. 6.4.4 Powering the Device From a Split-rail Configuration
      5. 6.4.5 Pin Strapping
        1. 6.4.5.1 Programming MSEL1
        2. 6.4.5.2 Programming PMB_ADDR
        3. 6.4.5.3 Programming MSEL2
        4. 6.4.5.4 Programming VSEL\FB
    5. 6.5 Programming
      1. 6.5.1 Supported PMBus Commands
  8. Register Maps
    1. 7.1  Conventions for Documenting Block Commands
    2. 7.2  (01h) OPERATION
    3. 7.3  (02h) ON_OFF_CONFIG
    4. 7.4  (03h) CLEAR_FAULTS
    5. 7.5  (04h) PHASE
    6. 7.6  (09h) P2_PLUS_WRITE
    7. 7.7  (0Ah) P2_PLUS_READ
    8. 7.8  (0Eh) PASSKEY
    9. 7.9  (10h) WRITE_PROTECT
    10. 7.10 (15h) STORE_USER_ALL
    11. 7.11 (16h) RESTORE_USER_ALL
    12. 7.12 (19h) CAPABILITY
    13. 7.13 (1Bh) SMBALERT_MASK
    14. 7.14 (20h) VOUT_MODE
    15. 7.15 (21h) VOUT_COMMAND
    16. 7.16 (22h) VOUT_TRIM
    17. 7.17 (24h) VOUT_MAX
    18. 7.18 (25h) VOUT_MARGIN_HIGH
    19. 7.19 (26h) VOUT_MARGIN_LOW
    20. 7.20 (27h) VOUT_TRANSITION_RATE
    21. 7.21 (29h) VOUT_SCALE_LOOP
    22. 7.22 (2Ah) VOUT_SCALE_MONITOR
    23. 7.23 (2Bh) VOUT_MIN
    24. 7.24 (33h) FREQUENCY_SWITCH
    25. 7.25 (35h) VIN_ON
    26. 7.26 (36h) VIN_OFF
    27. 7.27 (39h) IOUT_CAL_OFFSET
    28. 7.28 (40h) VOUT_OV_FAULT_LIMIT
    29. 7.29 (41h) VOUT_OV_FAULT_RESPONSE
    30. 7.30 (42h) VOUT_OV_WARN_LIMIT
    31. 7.31 (43h) VOUT_UV_WARN_LIMIT
    32. 7.32 (44h) VOUT_UV_FAULT_LIMIT
    33. 7.33 (45h) VOUT_UV_FAULT_RESPONSE
    34. 7.34 (46h) IOUT_OC_FAULT_LIMIT
    35. 7.35 (48h) IOUT_OC_LV_FAULT_LIMIT
    36. 7.36 (49h) IOUT_OC_LV_FAULT_RESPONSE
    37. 7.37 (4Ah) IOUT_OC_WARN_LIMIT
    38. 7.38 (4Fh) OT_FAULT_LIMIT
    39. 7.39 (50h) OT_FAULT_RESPONSE
    40. 7.40 (51h) OT_WARN_LIMIT
    41. 7.41 (55h) VIN_OV_FAULT_LIMIT
    42. 7.42 (60h) TON_DELAY
    43. 7.43 (61h) TON_RISE
    44. 7.44 (64h) TOFF_DELAY
    45. 7.45 (65h) TOFF_FALL
    46. 7.46 (78h) STATUS_BYTE
    47. 7.47 (79h) STATUS_WORD
    48. 7.48 (7Ah) STATUS_VOUT
    49. 7.49 (7Bh) STATUS_IOUT
    50. 7.50 (7Ch) STATUS_INPUT
    51. 7.51 (7Dh) STATUS_TEMPERATURE
    52. 7.52 (7Eh) STATUS_CML
    53. 7.53 (7Fh) STATUS_OTHER
    54. 7.54 (80h) STATUS_MFR_SPECIFIC
    55. 7.55 (88h) READ_VIN
    56. 7.56 (8Bh) READ_VOUT
    57. 7.57 (8Ch) READ_IOUT
    58. 7.58 (8Dh) READ_TEMPERATURE_1
    59. 7.59 (98h) PMBUS_REVISION
    60. 7.60 (99h) MFR_ID
    61. 7.61 (9Ah) MFR_MODEL
    62. 7.62 (9Bh) MFR_REVISION
    63. 7.63 (ADh) IC_DEVICE_ID
    64. 7.64 (AEh) IC_DEVICE_REV
    65. 7.65 (D1h) SYS_CFG_USER1
    66. 7.66 (D2h) PMBUS_ADDR
    67. 7.67 (D4h) COMP
    68. 7.68 (D5h) VBOOT_OFFSET_1
    69. 7.69 (D6h) STACK_CONFIG
    70. 7.70 (D8h) PIN_DETECT_OVERRIDE
    71. 7.71 (D9h) NVM_CHECKSUM
    72. 7.72 (DAh) READ_TELEMETRY
    73. 7.73 (79h) STATUS_ALL
    74. 7.74 (DDh) EXT_WRITE_PROTECTION
    75. 7.75 (A4h) IMON_CAL
    76. 7.76 (FCh) FUSION_ID0
    77. 7.77 (FDh) FUSION_ID1
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Input Capacitor Selection
        2. 8.2.3.2 Inductor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 Compensation Selection
        5. 8.2.3.5 VCC and VRDV Bypass Capacitors
        6. 8.2.3.6 BOOT Capacitor Selection
        7. 8.2.3.7 VOSNS and GOSNS Capacitor Selection
        8. 8.2.3.8 PMBus Address Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on TPS546C25EVM
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • VBD|33
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Programming PMB_ADDR

The pinstrapping table for PMB_ADDR is shown below. The PMBus address used can be sourced from PMBus register PMBus_ADDR instead of pinstrapping, depending on the state of the bit OVRD_PMB_ADDR in the PIN_DETECT_OVERRIDE register. When pinstrapping is used as the source of PMBus address, the contents of PMBus_ADDR indicating PMBus address (bits [14:8]) are updated with the pinstrapped values.

The table below shows the valid PMBus address configurations for primary and secondary devices through pinstrap.

Table 6-4 Allowed Combinations of PMB_ADDR
Single Phase Two Phase Three Phase Four Phase
All Resistor Values between 0Ω and 18.2kΩ

Primary: 22.1kΩ

Secondary: 0Ω

Primary: 49.9kΩ

First Secondary: 4.02kΩ

Second Secondary: 9.09kΩ

Primary: 137kΩ

First Secondary: 22.1kΩ

Second Secondary: 49.9kΩ

Third Secondary: 137kΩ

Primary: 26.7kΩ

Secondary: 2.21kΩ

Primary: 60.4kΩ

First Secondary: 4.87kΩ

Second Secondary: 11.3kΩ

Primary: 174kΩ

First Secondary: 26.7kΩ

Second Secondary: 60.4kΩ

Third Secondary: 174kΩ

Primary: 33.2kΩ

Secondary: 2.74kΩ

Primary: 76.8kΩ

First Secondary: 5.9kΩ

Second Secondary:14.3kΩ

Primary: 243kΩ

First Secondary: 33.2kΩ

Second Secondary: 76.8kΩ

Third Secondary: 243kΩ

Primary: 40.2kΩ

Secondary: 3.32kΩ

Primary: 102kΩ

First Secondary: 7.32kΩ

Second Secondary Secondary:18.2kΩ

Primary: > 412kΩ

First Secondary: 40.2kΩ

Second Secondary: 102kΩ

Third Secondary: > 412kΩ

Table 6-5 Resistor for Programming When MSEL1 Selects Primary = 1 (Primary Device)
RESISTOR (kΩ) Primary Stack Number MODE Common Address
< 1.78 Primary Device - 1 Phase Stack FCCM 11h
2.21 12h
2.74 13h
3.32 DCM 14h
4.02 15h
4.87 16h
5.9 FCCM 17h
7.32 18h
9.09 19h
11.3 DCM 1Ah
14.3 1Bh
18.2 1Ch
22.1 Primary Device - 2 Phase Stack FCCM 0Dh
26.7 0Eh
33.2 0Fh
40.2 10h
49.9 Primary Device - 3 Phase Stack 0Dh
60.4 0Eh
76.8 0Fh
102 10h
137 Primary Device - 4 Phase Stack 0Dh
174 0Eh
243 0Fh
> 412 10h
Table 6-6 Resistor for Programming When MSEL1 Selects Primary, Secondary = Secondary Device
RESISTOR (kΩ) Primary Stack Number MODE Common Address Unique Address
< 1.78 First Secondary Device - 2 Phase Stack FCCM 0Dh 1Dh
2.21 0Eh 1Eh
2.74 0Fh 1Fh
3.32 10h 20h
4.02 First Secondary Device - 3 Phase Stack 0Dh 1Dh
4.87 0Eh 1Eh
5.9 0Fh 1Fh
7.32 10h 20h
9.09 Second Secondary Device - 3 Phase Stack 0Dh 3Dh
11.3 0Eh 3Eh
14.3 0Fh 3Fh
18.2 10h 30h
22.1 First Secondary - 4 Phase Stack 0Dh 1Dh
26.7 0Eh 1Eh
33.2 0Fh 1Fh
40.2 10h 20h
49.9 Second Secondary - 4 Phase Stack 0Dh 3Dh
60.4 0Eh 3Eh
76.8 0Fh 3Fh
102 10h 30h
137 Third Secondary - 4 Phase Stack 0Dh 5Dh
174 0Eh 5Eh
243 0Fh 5Fh
> 412 10h 50h