SLVSHH4 July 2024 TPS546E25
ADVANCE INFORMATION
CMD Address | 46h |
Write Transaction: | Write Word |
Read Transaction: | Read Word |
Format: | LINEAR11 |
Phased: | Yes |
NVM Backup: | EEPROM or Pin Detection |
Updates: | On-the-fly |
The IOUT_OC_FAULT_LIMIT command sets the value of the output current that causes the overcurrent detector to indicate an overcurrent fault condition. The thresholds selected here are compared to the sensed low-side valley current. See Overcurrent Limit and Low-side Current Sense for more details.
Return to Supported PMBus Commands.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
R | R | R | R | R | R | R | R |
EXPONENT | IOUT_OC_FAULT_LIMIT | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R* or R/W** | R* or R/W** | R/W | R/W | R/W | R/W | R/W | R/W |
IOUT_OC_FAULT_LIMIT |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | Access | Reset | Description |
---|---|---|---|---|
15:11 | EXPONENT | R | 00000b | Linear format
two’s complement exponent. The exponent is
configured automatically through other settings,
with a result of 1b: 0.5A LSB 0b: 1A LSB |
10:8 | Reserved | R | 00000b | Not used and always set to 0. |
7 | IOUT_OC_FAULT_LIMIT | R* or R/W** | 0b |
* When STACK_NUMBER[1:0] = 1b, bit 7 is read only. ** When STACK_NUMBER[1:0] is >2b, bit 7 is readable and writeable as described in P2_PLUS_WRITE Commands and Response to P2_PLUS_READ Commands descriptions. |
6 | IOUT_OC_FAULT_LIMIT | R* or R/W*** | 0b |
* When STACK_NUMBER[1:0] = 1b, bit 6 is read only. ** When STACK_NUMBER[1:0] is >1b, bit 6 is readable and writeable as described in P2_PLUS_WRITE Commands and Response to P2_PLUS_READ Commands descriptions. |
5:0 | IOUT_OC_FAULT_LIMIT | R/W | NVM | These bits select the IOUT valley current limiting threshold. |
Every mantissa binary value in the writable bits is writeable and readable. However, the actual divider is set to the nearest supported value. Additionally, that mantissa value restored from EEPROM is fixed for each setting supported in hardware.
* Attempts to change the read-only bits (IOUT_OC_FAULT_LIMIT[15:8]) will be considered invalid/unsupported data when STACK_NUMBER[1:0] is = 1b. The device will NACK the unsupported data and the received value will be ignored. The ’cml’ bit in the STATUS_BYTE and the ‘ivd’ bit in the STATUS_CML registers will be set.
** Attempts to change the read-write bit (IOUT_OC_FAULT_LIMIT[7]) will only be considered valid data if STACK_NUMBER[1:0] is > 2b.
*** Attempts to change the read-write bit (IOUT_OC_FAULT_LIMIT[6]) will only be considered valid data if STACK_NUMBER[1:0] is > 1b.
IOUT_OC_FAULT_LIMIT [5:0] | IOUT_OC (A) | |
---|---|---|
Greater than or equal to | Less than | |
14d | 12.5 | |
14d | 17d | 15 |
17d | 22d | 18.75 |
22d | 25d | 23.75 |
25d | 28d | 26.25 |
28d | 33d | 30 (60%) |
33d | 37d | 35 |
37d | 39d | 37.5 |
39d | 42d | 40 (80%) |
42d | 47d | 43.75 |
47d | 50d | 48.75 |
50d | 53d | 50 (100%) |
53d | 58d | 55 |
58d | 60 |
When the PMBus host attempts to execute a P2+ write to IOUT_OC_FAULT_LIMIT with the PHASE data in the command set to FFh, the expectation is to equally divide the commanded net “Stack OC” level among the phases as their individual “Phase OC” settings. In order to achieve that, the device does the following:
3-ph STACK OC commanded[5:0] | PHASE IOUT_OC (A) | |
---|---|---|
Greater than or equal to | Less than | |
42d | 12.5 | |
42d | 51d | 15 |
51d | 64d | 18.75 |
64d | 75d | 23.75 |
75d | 85d | 26.25 |
85d | 98d | 30 (60%) |
98d | 109d | 35 |
109d | 117d | 37.5 |
117d | 126d | 40 (80%) |
126d | 139d | 43.75 |
139d | 148d | 48.75 |
148d | 158d | 50 (100%) |
158d | 173d | 55 |
173d | 60 |
When the PMBus host attempts to execute a P2+ read on IOUT_OC_FAULT_LIMIT with the PHASE data in the command set to FFh, only the primary device will respond to P2+ read commands with incoming data for PHASE=FFh. The primary device multiplies the IOUT_OC level by the STACK_NUMBER and reports the product back on the PMBus. For example, if the IOUT_OC is 24A for the primary phase in a 3-phase rail, then a P2+ read with PHASE=FFh will yield 24 x 3 = 72A as the read-back value.