SLVSHH4 July 2024 TPS546E25
ADVANCE INFORMATION
| CMD Address | 45h |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| NVM Backup: | EEPROM |
| Updates: | On-the-fly |
The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output under-voltage fault. The fault limit is programmed into VOUT_UV_FAULT_LIMIT. The device also:
Return to Supported PMBus Commands.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW | R | R/W | R/W | R/W | R | R/W | R/W |
| 0 | IGNRZ_UV | RS_UV | TD_UV | ||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7 | 0 | R | 0b | Not used and always set to 0. A write of 1 to this bit will result in an NACk and ivd. |
| 6 | IGNRZ_UV | RW | 1b | Output
undervoltage response setting 0b: The device continues operation (i.e., ignores the fault) without interruption (note that the bit[6] IGNRZ_UV is active low so that when IGNRZ_OV=0, the fault is ignored). 1b: The device continues to operate for the delay time specified by TD_UV. If the fault condition is still present at the end of the delay time, the unit responds as programmed in the Retry Setting. Note that if an UV fault occurred while IGNRZ_UV is set to ignore the fault (0b) and if the fault status was not cleared through CLEAR_FAULTS, and if IGNRZ_UV is changed to 1b, the device will respond to the previous fault as programmed in RS_UV and TD_UV. |
| 5:3 | RS_UV | RW | NVM | Output voltage
undervoltage retry setting. 000b: Latch-off after the fault. The device remains disabled until the fault is cleared. A VCC power cycle or EN toggle can restart the power conversion. 111b: Automatically restart after a 52ms delay, without limitation on the number of restart attempts, until it is commanded off or bias power is removed or another fault condition causes the unit to shutdown. Any value other than 000b or 111b will not be accepted and such an attempt shall be considered as invalid data or usupported data (ivd) and the device will respond as described in ivd. Since all 3 bits must be the same, only one bit (bit 5) is stored in EEPROM. |
| 2:0 | TD_UV | R | 000b | Output under
voltage retry response time delay setting. The
hiccup time is always 52ms, but the response can
be delayed with the following settings in bits
[1:0]. If the fault condition goes away before the
delay counter expires, then the delay counter is
reset to 0, and the output is not disabled. Bit 2
is read only and always 0. Writing a 1 to bit 2
will be ignored. 000b: 2 us 001b: 16 us 010b: 64 us 011b: 256 us |