Start-Up

The start-up and shutdown of the device is controlled by several PMBus programmable values including:

• (01h) OPERATION
• (02h) ON_OFF_CONFIG
• (60h) TON_DELAY
• (61h) TON_RISE
• (64h) TOFF_DELAY
• (65h) TOFF_FALL

The t_{ON_RISE} time is selectable by pin-strapping through MSEL1, PMBus programming, or both.

With the default ON_OFF_CONFIG settings, the timing is as shown. See the Supported PMBus commands for full details on the implementation and use.

Figure 6-4 TPS546E25 Start-Up and Shutdown

The startup sequence includes three sequential periods. During the first period, the device does initialization, which includes building up internal LDOs and references, register value initialization, pin strap detection, enabling digital interface, and so forth. The initialization, which is not gated by CTRL pin voltage, starts as long as VCC pin voltage is above the VCC_OK UVLO rising threshold (3.15V typical). The length of this period is about 200μs for TPS546E25 device. The PMBus communication including both read and write operations is allowed after finishing the initialization.

Once the CTRL pin voltage crosses above CTRL high threshold (typically 1.2V) the device moves to the second period, power-on delay. The power-on delay is programmable in TPS546E25 through register TON_DELAY with minimum 0.05ms delay and maximum 2ms delay.

The V_OUT soft start is the third period. A soft-start ramp, which is an internal signal, starts when the chosen power-on delay finishes. The soft-start time can be selected in register TON_RISE with options of 1ms, 2ms, 4ms, 8ms, and 16ms. When starting up without prebias on the output, the VOUT ramps up from 0V to either the selected Vboot value or the programmable VOUT_COMMAND value to avoid the inrush current by the output capacitor charging, and also minimize VOUT overshoot.

For the startup with a prebiased output the device limits current from being discharged from the prebiased output voltage by preventing the low-side FET from forcing the SW node low until after the first PWM pulse turns on the high-side FET. After the increasing reference voltage exceeds the feedback voltage, which is internally divided down from (VOSNS−GOSNS) level, the high-side SW pulses start. This action enables a smooth start-up with a prebiased output.

Shutdown

The TPS546E25 device also offers programmable soft-stop feature through PMBus register TOFF_FALL with 0.5ms, 1ms, 2ms, and 4ms options. The soft-stop feature forces a controlled decrease of the output voltage from regulation to 200mV. After Vout is discharged to 200mV level the power stage stops switching and goes to tri-state. There can be negative inductor current forced during the TOFF_FALL time to discharge the output voltage.

After a stop condition is received and the selected TOFF_DELAY delay expires, the TPS546E25 device enters the soft-stop operation during which the control loop actively controls the discharge slew rate of the output voltage. The power stage continues switching while the internal reference ramps down linearly. The discharge slew rate during this phase is determined by the selected boot up voltage (not the current output voltage) and the selected TOFF_FALL time. After Vout is discharged to 200mV level the power stage stops switching and goes to tri-state. The Vout discharge continues but the discharge slew rate is controlled by the load current. With this discharge operation, the TPS546E25 device controls the soft-stop slew rate rather the total soft-stop time, thus the total VOUT discharge time (also known as, soft-stop time) can vary from the register TOFF_FALL value. The TOFF_FALL time is utilized to set the internal reference DAC ramp-down time from the regulation level to 0mV. For example, under heavy load condition, the total soft-stop time from VOUT regulation level to zero volt is likely shorter than the programmed TOFF_FALL value. Under light load, the total soft-stop time likely becomes longer than the programmed TOFF_FALL value.