SLVSHH4 July 2024 TPS546E25
ADVANCE INFORMATION
CMD Address | 60h |
Write Transaction: | Write Word |
Read Transaction: | Read Word |
Format: | LINEAR11 |
Phased: | No |
NVM Backup: | EEPROM |
Updates: | On-the-fly |
The TON_DELAY command sets the time, in milliseconds, from when a start condition is received (as programmed by the ON_OFF_CONFIG command) until the output voltage starts to rise.
Return to Supported PMBus Commands.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
R | R | R | R | R | R | R | R |
EXPONENT | TON_DELAY | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R | R | R | R | R | RW | RW | RW |
TON_DELAY |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | Access | Reset | Description |
---|---|---|---|---|
15:11 | EXPONENT | R | 11111b | Linear format two’s complement exponent. The exponent is not programmable, with a result of 0.5ms LSB. |
10:3 | Reserved | R | 00000b | Not used and always set to 0. |
2:0 | TON_DELAY | R/W | 000b | These bits select the TON_DELAY time. When 000b is selected, a minimum 50us delay is enforced. |
Every mantissa binary value in the writable bits is writeable and readable. However, the actual divider is set to the nearest supported value. Additionally, that mantissa value restored from EEPROM is fixed for each setting supported in hardware.
Attempts to change the read-only bits (TON_DELAY[15:3]) will be considered invalid/unsupported data. The device will NACK the unsupported data and the received value will be ignored. The ’cml’ bit in the STATUS_BYTE and the ‘ivd’ bit in the (7Eh) STATUS_CML registers will be set.
TON_DELAY [2:0] | TON_DELAY (ms) | |
---|---|---|
Greater than or equal to | Less than | |
1d | 0.05 | |
1d | 2d | 0.5 |
2d | 3d | 1 |
3d | 8d | 2 |