SLVSHH4 July 2024 TPS546E25
ADVANCE INFORMATION
| CMD Address | 21h |
| Write Transaction: | Write Word |
| Read Transaction: | Read Word |
| Format: | ULINEAR16 per (20h) VOUT_MODE |
| NVM Back-up: | No (VBOOT_OFFSET_1) / VOUT_SCALE_LOOP |
| Updates: | on-the-fly |
The regulated output can be set by PMBus or by the result of pinstrapping on pin VSEL. When PMBus or pinstrapping is used to set the regulated voltage, the commanded output voltage in volts is determined by a combination of VOUT_COMMAND, VOUT_TRIM, VOUT_MARGIN_HIGH, VOUT_MARGIN_LOW, and OPERATION commands, as below. As stated in the description of the VOUT_MODE command, the VOUT step size is 1.953mV.
This register can be changed during soft-start or soft-stop. However, the rail will continue to ramp up/down to the original target (VBOOT) at the rate programmed into TON_RISE/TOFF_FALL. After soft-start completes (and if VOUT_COMMAND is different from the VBOOT value), the device will immediately transition from the VBOOT value to the latest written VOUT_COMMAND at the programmed VOUT_TRANSITION_RATE. Writes to VOUT_COMMAND during soft-stop will be acknowledged, however, no transition will occur and VOUT_COMMAND will get automatically updated back to VBOOT at the conclusion of soft-stop. After soft-start has completed, writes to VOUT_COMMAND are also allowed even if the output voltage is still transitioning to a previously programmed VOUT_COMMAND. The output voltage will immediately begin transitioning to the newly programmed VOUT_COMMAND at the rate specified by VOUT_TRANSITION_RATE. The device does not wait for the prior transition to complete.
Return to Supported PMBus Commands.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| R | R | R | R/W | R/W | R/W | R/W | R/W |
| VOUT_COMMAND (High Byte) | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| VOUT_COMMAND (Low Byte) | |||||||
The programmed Vout is computed as:
default*: XXX0 0000 0000 0000 (binary) (X means writes will be ignored and reads will be 0)
VOUT = (VOUT_COMMAND + VOUT_TRIM + (VOUT_MARGIN_HIGH – 1) * VOUT_COMMAND * OPERATION[5] – (1 – VOUT_MARGIN_LOW) * VOUT_COMMAND * OPERATION[4]) * VOUT_MODE
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 15:13 | VOUT_COMMAND | R | 000b | Not used and always set to 0. |
| 12:0 | VOUT_COMMAND | R/W | VBOOT_OFFSET_1 (see below) | Sets the output voltage target via the PMBus interface. |
At power up, the reset value of VOUT_COMMAND is derived from VBOOT_OFFSET_1 / VOUT_SCALE_LOOP . When the rail is disabled by the mechanism programmed to ON_OFF_CONFIG or due to a fault, the value in VOUT_COMMAND is updated to VBOOT.
When the PMB_ADDR/VORST# pin is configured as a RESET# pin in SYS_CONFIG_USER1 (EN_VORST), assertion of the PMB_ADDR/VORST# pin causes the output voltage to return to the VBOOT value in VBOOT_OFFSET_1 (VBOOT_1), and causes the VOUT_COMMAND value to be updated accordingly.
Writes to VOUT_COMMAND for which the resulting value, including any offset from VOUT_TRIM, is greater than the current (24h) VOUT_MAX or less than the current (2Bh) VOUT_MIN, causes the VOUT_COMMAND to move to the value specified by (2Bh) VOUT_MIN or (24h) VOUT_MAX respectively. The VOUT_MAX_MIN warning bit is set in STATUS_VOUT, which sets the appropriate bit in STATUS_WORD, and the host is notified per the PMBus 1.3.1 Part II specification, section 10.2.