SLVSHH4 July 2024 TPS546E25
ADVANCE INFORMATION
| CMD Address: | 1Bh |
| Write Transaction: | Write Word |
| Read Transaction: | Block Write-Block Read Process Call |
| Format: | Write: Unsigned
Binary (2 bytes) Read: Unsigned Binary (1 byte) |
| NVM Back-up: | EEPROM |
| Updates: | On-the-fly |
The SMBALERT_MASK command can be used to prevent a warning or fault condition from asserting the SMB_ALERT# signal. Setting a MASK bit does not prevent the associated bit in the STATUS_x command from being set, but prevents the associated bit in the STATUS_x command from asserting SMB_ALERT#. The following register descriptions describe the individual mask bits available.
SMBALERT_MASK write transaction is Write Word with the following:
SMBALERT_MASK read transaction is a Block Write-Block Read Process Call with the following:
Please refer to the PMBus 1.3.1 Part II specification, section 15.38 SMBALERT_MASK Command for further details on this command, and the SMBus 3.1 specification, section 6.5.8 Block Write-Block Read Process Call for further details on the process call transaction.
STATUS_BYTE added and STATUS_WORD extended per new requirement in PMBus 1.4 Section 15.38.
Writing to a mask bit marked with an X with either a 0 or 1 will not cause an IVD error in (7Eh) STATUS_CML. A bit marked with ‘X’ will default to a mask value of ‘1’ and is incapable of ever asserting SMBALERT# (most commonly these are un-supported read-only logic 0 status bit positions. Attempting to read or write a mask byte for any STATUS_X command code other than this list shall be considered as invalid data or unsupported data (IVD) error in (7Eh) STATUS_CML
For all registers, a 0b indicates that SMB_ALERT# will be asserted when the condition happens, and a 1b indicates that SMB_ALERT# will not be asserted when the condition happens.
Return to Supported PMBus Commands.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R | R | R/W | R/W | R | R/W | R/W | R/W |
| 0 | MASK_OFF | MASK_OVF | MASK_OCF | 0 | MASK_OTFW | MASK_CML | MASK_OTH |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| R/W | R/W | R/W | R/W | R | R | R/W | R |
| MASK_VFW | MASK_OCFW | MASK_INPUT | MASK_MFR | MASK_PGOOD_Z | 0 | MASK_OTHER | 0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R | R | R | R | R | R | R | R |
| STATUS_BYTE | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R/W | R/W | R/W | R/W | R/W | R | R | R |
| MASK_OVF | MASK_OVW | MASK_UVW | MASK_UVF | MASK_VO_MAX_MIN_W | 0 | 0 | 0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R/W | R | R/W | R/W | R | R | R | R |
| MASK_OCF | MASK_OCUV | MASK_OCW | MASK_UCF | 0 | 0 | 0 | 0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R/W | R | R | R | R/W | R | R | R |
| PVIN_OVF | 0 | 0 | 0 | LOW_VIN | 0 | 0 | 0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R/W | R/W | R | R | R | R | R | R |
| OTF_PROG | OTW_PROG | 0 | 0 | 0 | 0 | 0 | 0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R/W | R/W | R/W | R/W | R | R | R/W | R |
| MASK_IVC | MASK_IVD | MASK_PEC | MASK_MEM | 0 | 0 | MASK_OTHER | 0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R | R | R | R | R | R | R | R/W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | MASK_FRST_2_ALRT |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R/W | R/W | R/W | R/W | R | R | R/W | R/W |
| MASK_DCM | MASK_OTF_BG | MASK_PS_FLT | MASK_PS_COMM_WRN | 0 | 0 | MASK_PS_OT | MASK_PS_UV |
Return to Supported PMBus Commands.