SLVSB14B October   2011  – February 2016 TPS54821

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed Frequency PWM Control
      2. 7.3.2 Continuous Current Mode Operation (CCM)
      3. 7.3.3 VIN and Power VIN Pins (VIN and PVIN)
      4. 7.3.4 Voltage Reference
      5. 7.3.5 Adjusting the Output Voltage
      6. 7.3.6 Safe Start-up into Pre-Biased Outputs
      7. 7.3.7 Error Amplifier
      8. 7.3.8 Slope Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1  Enable and Adjusting Undervoltage Lockout
      2. 7.4.2  Adjustable Switching Frequency and Synchronization (RT/CLK)
      3. 7.4.3  Adjustable Switching Frequency (RT Mode)
      4. 7.4.4  Synchronization (CLK mode)
      5. 7.4.5  Slow Start (SS/TR)
      6. 7.4.6  Power Good (PWRGD)
      7. 7.4.7  Bootstrap Voltage (BOOT) and Low Dropout Operation
      8. 7.4.8  Sequencing (SS/TR)
      9. 7.4.9  Output Overvoltage Protection (OVP)
      10. 7.4.10 Overcurrent Protection
      11. 7.4.11 Thermal Shutdown
      12. 7.4.12 Small Signal Model for Loop Response
      13. 7.4.13 Simple Small Signal Model for Peak Current Mode Control
      14. 7.4.14 Small Signal Model for Frequency Compensation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Parameters
      2. 8.2.2 Design Guide - Step-By-Step Design Procedure
        1. 8.2.2.1  Typical Application Schematic
        2. 8.2.2.2  Operating Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Slow Start Capacitor Selection
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Under Voltage Lockout Set Point
        9. 8.2.2.9  Output Voltage Feedback Resistor Selection
          1. 8.2.2.9.1 Minimum Output Voltage
        10. 8.2.2.10 Compensation Component Selection
        11. 8.2.2.11 Fast Transient Considerations
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 PCB Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Estimated Circuit Area
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input Voltage VIN –0.3 20 V
PVIN –0.3 20
EN –0.3 6
BOOT –0.3 27
VSENSE –0.3 3
COMP –0.3 3
PWRGD –0.3 6
SS/TR –0.3 3
RT/CLK –0.3 6
Output Voltage BOOT-PH 0 7.5 V
PH –1 20
PH 10ns Transient –3 20
Vdiff (GND to exposed thermal pad) –0.2 0.2 V
Source Current RT/CLK ±100 µA
PH Current Limit A
Sink Current PH Current Limit A
PVIN Current Limit
COMP ±200 µA
PWRGD –0.1 5 mA
Operating Junction Temperature IOUT = 8 A –40 125 °C
IOUT = 6 A –40 150
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Input voltage range VIN 4.5 17 V
Power stage input voltage range PVIN 1.6 17 V
Output current TJ = –40°C to 125°C 0 8 A
Operating junction temperature, TJ IOUT = 6 A –40 150 °C
IOUT = 8 A –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1)(2) TPS54821 UNITS
RHL (14 PINS)
RθJA Junction-to-ambient thermal resistance 47.2 °C/W
RθJA Junction-to-ambient thermal resistance(3) 32
RθJCtop Junction-to-case (top) thermal resistance 64.8
RθJB Junction-to-board thermal resistance 14.4
ψJT Junction-to-top characterization parameter 0.5
ψJB Junction-to-board characterization parameter 14.7
RθJCbot Junction-to-case (bottom) thermal resistance 3.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more information.
(3) Test board conditions:
  1. 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch
  2. 2 oz. copper traces located on the top of the PCB
  3. 2 oz. copper ground planes on the 2 internal layers and bottom layer
  4. 4 0.010 inch thermal vias located under the device package

6.5 Electrical Characteristics

TJ = –40°C to 125°C, VIN = 4.5V to 17V, PVIN = 1.6V to 17V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN AND PVIN PINS)
PVIN operating input voltage 1.6 17 V
VIN operating input voltage 4.5 17 V
VIN internal UVLO threshold VIN rising 4.0 4.5 V
VIN internal UVLO hysteresis 150 mV
VIN shutdown supply Current EN = 0 V 2 5 μA
VIN operating – non switching supply current VSENSE = 610 mV 600 800 μA
ENABLE AND UVLO (EN PIN)
Enable threshold Rising 1.21 1.26 V
Enable threshold Falling 1.10 1.17
Input current EN = 1.1 V 1.15 μA
Hysteresis current EN = 1.3 V 3.3 μA
VOLTAGE REFERENCE
Voltage reference 0 A ≤ IOUT ≤ 8A 0.594 0.6 0.606 V
MOSFET
High-side switch resistance BOOT-PH = 3 V 32 60 mΩ
High-side switch resistance(1) BOOT-PH = 6 V 26 40 mΩ
Low-side Switch Resistance(1) VIN = 12 V 19 30 mΩ
ERROR AMPLIFIER
Error amplifier Transconductance (gm) –2 μA < ICOMP < 2 μA, V(COMP) = 1 V 1300 μMhos
Error amplifier dc gain VSENSE = 0.6 V 1000 4000 V/V
Error amplifier source/sink V(COMP) = 1 V, 100 mV input overdrive ±110 μA
Start switching threshold 0.25 V
COMP to Iswitch gm 21 A/V
CURRENT LIMIT
High-side switch current limit threshold 10.5 14.5 17 A
Low-side switch sourcing current limit 9.5 11.5 15 A
Low-side switch sinking current limit 2 3 4 A
Hiccup wait time 512 Cycles
Hiccup time before re-start 16384 Cycles
THERMAL SHUTDOWN
Thermal shutdown 160 175 °C
Thermal shutdown hysteresis 10 °C
Thermal shutdown hiccup time 16384 Cycles
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Minimum switching frequency Rrt = 240 kΩ (1%) 160 200 240 kHz
Switching frequency Rrt = 100 kΩ (1%) 400 480 560 kHz
Maximum switching frequency Rrt = 29 kΩ (1%) 1440 1600 1760 kHz
Minimum pulse width 20 ns
RT/CLK high threshold 2 V
RT/CLK low threshold 0.78 V
RT/CLK falling edge to PH rising edge delay Measure at 500 kHz with RT resistor in series 66 ns
Switching frequency range (RT mode set point and PLL mode) 200 1600 kHz
PH (PH PIN)
Minimum on time Measured at 90% to 90% of VIN, 25°C, IPH = 2A 94 145 ns
Minimum off time BOOT-PH ≥ 3 V 0 ns
BOOT (BOOT PIN)
BOOT-PH UVLO 2.1 3 V
SLOW START AND TRACKING (SS/TR PIN)
SS charge current 2.3 μA
SS/TR to VSENSE matching V(SS/TR) = 0.4 V 20 60 mV
POWER GOOD (PWRGD PIN)
VSENSE threshold VSENSE falling (Fault) 92 % Vref
VSENSE rising (Good) 94 % Vref
VSENSE rising (Fault) 106 % Vref
VSENSE falling (Good) 104 % Vref
Output high leakage VSENSE = Vref, V(PWRGD) = 5.5 V 30 100 nA
Output low I(PWRGD) = 2 mA 0.3 V
Minimum VIN for valid output V(PWRGD) < 0.5V at 100 μA 0.6 1 V
Minimum SS/TR voltage for PWRGD 1.4 V
(1) Measured at pins

6.6 Typical Characteristics

TPS54821 hsrdson_tj_lvsb14.gif
Figure 1. High-side MOSFET on Resistance
vs Junction Temperature
TPS54821 vref_tj_lvsb14.gif
Figure 3. Voltage Reference vs Junction Temperature
TPS54821 uvlo_tj_lvsb14.gif
Figure 5. EN Pin UVLO Threshold
vs Junction Temperature
TPS54821 pin_pullup_lvsb14.gif
Figure 7. EN Pin Pullup Current Threshold
vs Junction Temperature
TPS54821 iq_vi_lvsb14.gif
Figure 9. VIN Non-Switching Operating Quiescent Current
vs Input Voltage
TPS54821 sstr_junc_lvsb14.gif
Figure 11. SS/TR Vsense Offset vs Junction Temperature
TPS54821 hi_sd_cur_vi_lvsb14.gif
Figure 13. High-side Current Limit Threshold
vs Input Voltage
TPS54821 mincon_duty_lvsb14.gif
Figure 15. Minimum Controllable Duty Ratio
vs Junction Temperature
TPS54821 lsrdson_tj_lvsb14.gif
Figure 2. Low-side MOSFET on Resistance
vs Junction Temperature
TPS54821 fsw_tj_lvsb14.gif
Figure 4. Oscillator Frequency vs Junction Temperature
TPS54821 hys_tj_lvsb14.gif
Figure 6. EN Pin Hysteresis Current
vs Junction Temperature
TPS54821 sdqi_vi_lvsb14.gif
Figure 8. Shutdown Quiescent Current
vs Input Voltage
TPS54821 ss_tj_lvsb14.gif
Figure 10. Slow Start Charge Current
vs Junction Temperature
TPS54821 pwrgd_junc_lvsb14.gif
Figure 12. PWRGD Threshold vs Junction Temperature
TPS54821 t_tj_lvsb14.gif
Figure 14. Minimum Controllable on Time
vs Junction Temperature
TPS54821 boot_tj_lvsb14.gif
Figure 16. BOOTH-PH UVLO Threshold
vs Junction Temperature