space
The TPS54824 is a full-featured 17-V (19-V maximum), 8-A synchronous step-down DC/DC converter in a 3.5 mm × 3.5 mm HotRod™ QFN package.
The device is optimized for small solution size through high efficiency and integrating the high-side and low-side MOSFETs. Further space savings are achieved through peak current mode control, which reduces component count, and by selecting a high switching frequency, reducing the inductor footprint.
The peak current mode control simplifies the loop compensation and provides fast transient response. Cycle-by-cycle peak current limiting on the high-side and low-side sourcing current limit protects the device in overload situations. Hiccup limits MOSFET power dissipation if a short circuit or over loading fault persists.
A power good supervisor circuit monitors the regulator output. The PGOOD pin is an open-drain output and goes high impedance when the output voltage is in regulation. An internal deglitch time prevents the PGOOD pin from pulling low unless a fault has occurred.
A dedicated EN pin can be used to control the regulator on/off and adjust the input undervoltage lockout. The output voltage start-up ramp is controlled by the SS/TRK pin, which allows operation as either a standalone power supply or in tracking situations.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS54824 | RNV (18) | 3.50 mm × 3.50 mm |
Changes from A Revision (February 2017) to B Revision
Changes from * Revision (November 2016) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
BOOT | 1 | I | Floating supply voltage for high-side MOSFET gate drive circuit. Connect a 0.1-µF ceramic capacitor between BOOT and SW pins. |
VIN | 2, 11 | I | Input voltage supply pin. Power for the internal circuit and the connection to drain of high-side MOSFET. Connect both pins to the input power source with a low impedance connection. Connect both pins and their neighboring PGND pins. |
PGND | 3, 4, 5, 8, 9, 10 | – | Ground return for low-side power MOSFET and its drivers. |
SW | 6, 7 | O | Switching node. Connected to the source of the high-side MOSFET and drain of the low-side MOSFET. |
AGND | 12 | – | Ground of internal analog circuitry. AGND must be connected to the PGND plane. |
RT/CLK | 13 | I | Switching frequency setting pin. In RT mode, an external timing resistor adjusts the switching frequency. In CLK mode, the device synchronizes to an external clock input to this pin. |
FB | 14 | I | Converter feedback input. Connect to the output voltage with a resistor divider. |
COMP | 15 | I | Error amplifier output and input to the PWM modulator. Connect loop compensation to this pin. |
SS/TRK | 16 | I | Soft-start and tracking pin. Connecting an external capacitor sets the soft-start time. This pin can also be used for tracking and sequencing. |
EN | 17 | I | Enable pin. Float or pull high to enable the device. Connect a resistor divider to this pin to implement adjustable under voltage lockout and hysteresis. |
PGOOD | 18 | O | Open-drain power good indicator. It is asserted low if output voltage is outside if the PGOOD thresholds, VIN is low, EN is low, device is in thermal shutdown or device is in soft-start. |