SLVSDC9B November   2016  – November 2019 TPS54824

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Simplified Schematic
  3. 3 Description
    1.     Efficiency
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Continuous Conduction Mode Operation (CCM)
      3. 7.3.3  VIN Pins and VIN UVLO
      4. 7.3.4  Voltage Reference and Adjusting the Output Voltage
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Enable and Adjustable UVLO
      7. 7.3.7  Soft Start and Tracking
      8. 7.3.8  Safe Start-up into Pre-Biased Outputs
      9. 7.3.9  Power Good
      10. 7.3.10 Sequencing (SS/TRK)
      11. 7.3.11 Adjustable Switching Frequency (RT Mode)
      12. 7.3.12 Synchronization (CLK Mode)
      13. 7.3.13 Bootstrap Voltage and 100% Duty Cycle Operation (BOOT)
      14. 7.3.14 Output Overvoltage Protection (OVP)
      15. 7.3.15 Overcurrent Protection
        1. 7.3.15.1 High-side MOSFET Overcurrent Protection
        2. 7.3.15.2 Low-side MOSFET Overcurrent Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Inductor Selection
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Input Capacitor
        5. 8.2.2.5  Output Voltage Resistors Selection
        6. 8.2.2.6  Soft-start Capacitor Selection
        7. 8.2.2.7  Undervoltage Lockout Set Point
        8. 8.2.2.8  Bootstrap Capacitor Selection
        9. 8.2.2.9  PGOOD Pull-up Resistor
        10. 8.2.2.10 Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Alternate Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.10 Compensation

There are several methods used to compensate DC - DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation internal to the device. Because the slope compensation is ignored, the actual cross-over frequency will usually be lower than the cross-over frequency used in the calculations. This method assumes the cross-over frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole. This is the case when using low ESR output capacitors. Use the WEBENCH® software for more accurate loop compensation. These tools include a more comprehensive model of the control loop.

To get started, the modulator pole, fpmod, and the ESR zero, fz1 must be calculated using Equation 26 and Equation 27. For Cout, use a derated value of 116 μF and an ESR of 1 mΩ. Use equations Equation 28 and Equation 29, to estimate a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is 6.1 kHz and fzmod is 1370 kHz. Equation 28 is the geometric mean of the modulator pole and the ESR zero. Equation 29 is the mean of modulator pole and one half the switching frequency. Equation 28 yields 92 kHz and Equation 29 gives 46 kHz. Use the lower value of Equation 28 or Equation 29 for an initial crossover frequency. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole.

Equation 26. TPS54824 eq43_lvs795.gif

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Equation 27. TPS54824 eq44_lvs795.gif

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Equation 28. TPS54824 eq45_lvs919.gif

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Equation 29. TPS54824 eq46_lvs919.gif

To determine the compensation resistor, R5, use Equation 30. R5 is calculated to be 5.71 kΩ and the closest standard value 5.76 kΩ. Use Equation 31 to set the compensation zero to the modulator pole frequency. Equation 31 yields 4500 pF for compensating capacitor C18 and the closest standard value is 4700 pF.

Equation 30. TPS54824 Rcomp_SCO3.gif

Where:

  • Power stage transconductance, gmPS = 16 A/V
  • VOUT = 1.8 V
  • VREF = 0.6 V
  • Error amplifier transconductance, gmEA = 1100 µA/V
Equation 31. TPS54824 Ccomp_SCO3.gif

A compensation pole is implemented using an additional capacitor C17 in parallel with the series combination of R5 and C18. This capacitor is recommended to help filter any noise that may couple to the COMP voltage signal. Use the larger value of Equation 32 and Equation 33 to calculate the C17 and to set the compensation pole. C17 is calculated to be the largest of 20 pF and 79 pF. The closest standard value is 82 pF.

Equation 32. TPS54824 Chfesr_SCO3.gif

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Equation 33. TPS54824 Chffsw_SCO3.gif

Type III compensation can be used by adding the feed forward capacitor C19 in parallel with the upper feedback resistor. Type III compensation adds phase boost above what is possible from type II compensation because it places an additional zero/pole pair. The zero/pole pair is not independent. As a result once the zero location is chosen, the pole is fixed as well. The zero is placed at 1/2 the fSW by calculating the value of C19 with Equation 34. The calculated value is 37 pF and the closest standard value is 39 pF. It is possible to use larger feed forward capacitors to further improve the transient response but care should be taken to ensure there is a minimum of -10 dB gain margin at 1/2 the fSW in all operating conditions. The feed forward capacitor injects noise on the output into the FB pin and this added noise can result in more jitter at the switching node. To little gain margin can cause a repeated wide and narrow pulse behavior. This example design does not use the optional feedforward capacitor.

Equation 34. TPS54824 EQ_Cff_SLVSDV8.gif

The initial compensation based on these calculations is R5 = 5.76 kΩ, C18 = 4700 pF, C17 = 82 pF and C19 = 39 pF. These values yield a stable design but after testing the real circuit these values were changed to target a higher crossover frequency to improve transient response performance. The crossover frequency is increased by increasing the value of R5 and decreasing the value of the compensation capacitors. The final values used in this example are R5 = 9.53 kΩ, C18 = 2200 pF, C17 = 27 pF and C19 = 100 pF.