Figure 7-3 Internal RAMP Generation Circuit

The TPS548B28 uses D-CAP3 control mode to achieve the fast load transient while maintaining the ease-of-use feature. The D-CAP3 control mode architecture includes an internal ripple generation network enabling the use of very low-ESR output capacitors such as multi-layered ceramic capacitors (MLCC) and low-ESR polymer capacitors. No external current sensing network or voltage compensators are required with D-CAP3 control mode architecture. The role of the internal ripple generation network is to emulate the ripple component of the inductor current information and then combine it with the voltage feedback signal to regulate the loop operation. The amplitude of the ramp is determined by V_IN, V_OUT, operating frequency, and the R-C time-constant of the internal ramp circuit. At different switching frequency settings (see Table 7-1), the R-C time-constant varies to maintain relatively constant ramp amplitude. Also, the device uses internal circuitry to cancel the dc offset caused by injected ramp, and significantly reduces the dc offset caused by the output ripple voltage, especially under light load condition.

For any control topologies supporting no external compensation design, there is a minimum range, maximum range, or both, of the output filter it can support. The output filter used with the TPS548B28 is a low-pass L-C circuit. This L-C filter has double pole that is described in Equation 3.

Equation 3.

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS548B28. The low frequency L-C double pole has a 180-degree drop in phase. At the output filter frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal ripple generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per decade and increases the phase by 90 degrees per decade above the zero frequency.

After identifying the application requirements, the output inductance must be designed so that the inductor peak-to-peak ripple current is approximately between 15% and 40% of the maximum output current.

The inductor and capacitor selected for the output filter must be such that the double pole of Equation 3 is located no higher than 1/30th of operating frequency. Choose very small output capacitance leads to relatively high frequency L-C double pole, which allows that overall loop gain stays high until the L-C double frequency. Given the zero from the internal ripple generation network is relatively high frequency as well, the loop with very small output capacitance can have too high crossover frequency which is not desired. Use Table 7-2 to help locate the internal zero based on the selected switching frequency.

In general, where reasonable (or smaller) output capacitance is desired, output ripple requirement and load transient requirements can be used to determine the necessary output capacitance for stable operation.

For the maximum output capacitance recommendation, select the inductor and capacitor values so that the L-C double pole frequency is no less than 1/100th of operating frequency. With this starting point, verify the small signal response on the board using the phase margin at the loop crossover is greater than 50 degrees.

The actual maximum output capacitance can go higher as long as phase margin is greater than 50 degrees. However, small signal measurement (bode plot) must be done to confirm the design.

If MLCC is used, consider the derating characteristics to determine the final output capacitance for the design. For example, when using an MLCC with specifications of 10 µF, X5R and 6.3 V, the derating by DC bias and AC bias are 80% and 50%, respectively. The effective derating is the product of these two factors, which in this case is 40% and 4 µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be used in the system/applications.

For higher output voltage at or above 2 V, additional phase boost can be required to secure sufficient phase margin due to phase delay/loss for higher output voltage (large on-time (t_ON)) setting in a fixed-on-time topology based operation. A feedforward capacitor placed in parallel with R_{FB_HS} is found to be very effective to boost the phase margin at loop crossover. Refer to the Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor application report for details.

Besides boosting the phase, a feedforward capacitor feeds more V_OUT node information into FB node by the AC coupling. This feedforward during load transient event enables the control loop a faster response to V_OUT deviation. However, this feedforward during steady state operation also feeds more V_OUT ripple and noise into FB. High ripple and noise on FB usually leads to more jitter, or even double pulse behavior. To determine the final feedforward capacitor value, impacts to phase margin, load transient performance, and ripple and nosie on FB must be all considered. Using Frequency Analysis equipment to measure the crossover frequency and the phase margin is recommended.