SLUSCI8A July   2016  – August 2017 TPS548D21

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 40-A FET
      2. 7.3.2 On-Resistance
      3. 7.3.3 Package Size, Efficiency and Thermal Performance
      4. 7.3.4 Soft-Start Operation
      5. 7.3.5 VDD Supply Undervoltage Lockout (UVLO) Protection
      6. 7.3.6 EN_UVLO Pin Functionality
      7. 7.3.7 Fault Protections
        1. 7.3.7.1 Current Limit (ILIM) Functionality
        2. 7.3.7.2 VDD Undervoltage Lockout (UVLO)
        3. 7.3.7.3 Overvoltage Protection (OVP) and Undervoltage Protection (UVP)
        4. 7.3.7.4 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 DCAP3 Control Topology
      2. 7.4.2 DCAP Control Topology
    5. 7.5 Programming
      1. 7.5.1 AVSO
      2. 7.5.2 Programmable Pin-Strap Settings
        1. 7.5.2.1 Frequency Selection (FSEL) Pin
        2. 7.5.2.2 VSEL Pin
        3. 7.5.2.3 DCAP3 Control and Mode Selection
        4. 7.5.2.4 Application Workaround to Support 4-ms and 8-ms SS Settings
      3. 7.5.3 Programmable Analog Configurations
        1. 7.5.3.1 RSP/RSN Remote Sensing Functionality
          1. 7.5.3.1.1 Output Differential Remote Sensing Amplifier
        2. 7.5.3.2 Power Good (PGOOD Pin) Functionality
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS548D21 1.5-V to 16-V Input, 1-V Output, 40-A Converter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Design Procedure
        1. 8.2.3.1  Custom Design With WEBENCH® Tools
        2. 8.2.3.2  Switching Frequency Selection
        3. 8.2.3.3  Inductor Selection
        4. 8.2.3.4  Output Capacitor Selection
          1. 8.2.3.4.1 Minimum Output Capacitance to Ensure Stability
          2. 8.2.3.4.2 Response to a Load Transient
          3. 8.2.3.4.3 Output Voltage Ripple
        5. 8.2.3.5  Input Capacitor Selection
        6. 8.2.3.6  Bootstrap Capacitor Selection
        7. 8.2.3.7  BP Pin
        8. 8.2.3.8  R-C Snubber and VIN Pin High-Frequency Bypass
        9. 8.2.3.9  Optimize Reference Voltage (VSEL)
        10. 8.2.3.10 MODE Pin Selection
        11. 8.2.3.11 Overcurrent Limit Design.
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Mounting and Thermal Profile Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Custom Design With WEBENCH® Tools
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RVF|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RVF Package
40-Pin LQFN-CLIP With Thermal Pad
Top View
TPS548D21 pinout_SLUSCI8.gif

Pin Functions

PIN I/O/P(1) DESCRIPTION
NAME NO.
AGND 30 G Ground pin for internal analog circuits.
BOOT 5 P Supply rail for high-side gate driver (boot terminal). Connect boot capacitor from this pin to SW node. Internally connected to BP via bootstrap PMOS switch.
BP 31 O LDO output
DRGND 29 P Internal gate driver return.
EN_UVLO 4 I Enable pin that can turn on the DC/DC switching converter. Use also to program the required PVIN UVLO when PVIN and VDD are connected together.
FSEL 32 I Program switching frequency, internal ramp amplitude and FCCM mode.
ILIM 36 I/O Program overcurrent limit by connecting a resistor to ground.
MODE 34 I Mode selection pin. Select the control mode (DCAP3 or DCAP), internal VREF operation, and soft-start timing selection.
NC 27 No connect.
NU 1, 2, 3 O Not used pins.
PGND 13, 14, 15, 16, 17, 18, 19, 20 P Power ground of internal FETs.
PGOOD 35 O Open drain power good status signal.
PVIN 21, 22, 23, 24, 25, 26 P Power supply input for integrated power MOSFET pair.
RSN 38 I Inverting input of the differential remote sense amplifier.
RSP 39 I Non-inverting input of the differential remote sense amplifier.
REFIN_TRK 37 I System reference voltage that can be overridden by the external voltage source for tracking and sequencing application.
SW 6 , 7, 8, 9, 10, 11, 12 I/O Output switching terminal of power converter. Connect the pins to the output inductor.
VDD 28 P Controller power supply input.
VOSNS 40 I Output voltage monitor input pin.
VSEL 33 I Program the initial start-up and or reference voltage without feedback resistor dividers (from 0.6 V to 1.2 V in 50-mV increments).
(1) I = input, O = output, G = GND