SLUSC70D
March 2016 – July 2017
TPS548D22
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Simplified Application
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
40-A FET
7.3.2
On-Resistance
7.3.3
Package Size, Efficiency and Thermal Performance
7.3.4
Soft-Start Operation
7.3.5
VDD Supply Undervoltage Lockout (UVLO) Protection
7.3.6
EN_UVLO Pin Functionality
7.3.7
Fault Protections
7.3.7.1
Current Limit (ILIM) Functionality
7.3.7.2
VDD Undervoltage Lockout (UVLO)
7.3.7.3
Overvoltage Protection (OVP) and Undervoltage Protection (UVP)
7.3.7.4
Out-of-Bounds Operation
7.3.7.5
Overtemperature Protection
7.4
Device Functional Modes
7.4.1
DCAP3 Control Topology
7.4.2
DCAP Control Topology
7.5
Programming
7.5.1
Programmable Pin-Strap Settings
7.5.1.1
Frequency Selection (FSEL) Pin
7.5.1.2
VSEL Pin
7.5.1.3
DCAP3 Control and Mode Selection
7.5.1.3.1
Application Workaround to Support 4-ms and 8-ms SS Settings
7.5.2
Programmable Analog Configurations
7.5.2.1
RSP/RSN Remote Sensing Functionality
7.5.2.1.1
Output Differential Remote Sensing Amplifier
7.5.2.2
Power Good (PGOOD Pin) Functionality
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
TPS548D22 1.5-V to 16-V Input, 1-V Output, 40-A Converter
8.2.2
Design Requirements
8.2.3
Design Procedure
8.2.3.1
Switching Frequency Selection
8.2.3.2
Inductor Selection
8.2.3.3
Output Capacitor Selection
8.2.3.3.1
Minimum Output Capacitance to Ensure Stability
8.2.3.3.2
Response to a Load Transient
8.2.3.3.3
Output Voltage Ripple
8.2.3.4
Input Capacitor Selection
8.2.3.5
Bootstrap Capacitor Selection
8.2.3.6
BP Pin
8.2.3.7
R-C Snubber and VIN Pin High-Frequency Bypass
8.2.3.8
Optimize Reference Voltage (VSEL)
8.2.3.9
MODE Pin Selection
8.2.3.10
Overcurrent Limit Design.
8.2.4
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
10.2.1
Mounting and Thermal Profile Recommendation
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.2
Receiving Notification of Documentation Updates
11.3
Community Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RVF|40
MPQF268C
Thermal pad, mechanical data (Package|Pins)
RVF|40
QFND333E
Orderable Information
slusc70d_oa
slusc70d_pm
1
Features
Conversion
Input Voltage Range (PV
IN
): 1.5 V to 16 V
Input Bias Voltage (V
DD
) Range: 4.5 V to 22 V
Output Voltage Range: 0.6 V to 5.5 V
Integrated, 2.9-mΩ and 1.2-mΩ Power MOSFETs With 40-A Continuous Output Current
Voltage Reference 0.6 V to 1.2 V in 50-mV Steps Using VSEL Pin
±0.5%, 0.9-V
REF
Tolerance Range: –40°C to +125°C Junction Temperature
True Differential Remote Sense Amplifier
D-CAP3™ Control Loop
to Support Large Bulk Capacitors and/or Small MLCCs Without External Compensation
Adaptive On-Time Control with 4 Selectable Frequency Settings: 425 kHz, 650 kHz, 875 kHz, and 1.05 MHz
Temperature Compensated and Programmable Current Limit with R
ILIM
and OC Clamp
Choice of Hiccup or Latch-Off OVP or UVP
VDD UVLO External Adjustment by Precision EN Hysteresis
Prebias Start-up Support
Eco-mode™ and FCCM Selectable
Full Suite of Fault Protection and PGOOD