SLUSC79A November   2015  – December 2015 TPS549A20

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Thermal Information
    6. 6.6 Typical Characteristics
    7. 6.7 Thermal Performance
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  Powergood
      2. 7.3.2  D-CAP3 Control and Mode Selection
      3. 7.3.3  D-CAP3 Mode
      4. 7.3.4  Sample and Hold Circuitry
      5. 7.3.5  Adaptive Zero-Crossing
      6. 7.3.6  Forced Continuous-Conduction Mode
      7. 7.3.7  Current Sense and Overcurrent Protection
      8. 7.3.8  Overvoltage and Undervoltage Protection
      9. 7.3.9  Out-of-Bounds Operation (OOB)
      10. 7.3.10 UVLO Protection
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-Mode Light-Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
    5. 7.5 Programming
      1. 7.5.1  The PMBus General Descriptions
      2. 7.5.2  PMBus Slave Address Selection
      3. 7.5.3  PMBus Address Selection
      4. 7.5.4  Supported Formats
        1. 7.5.4.1 Direct Format: Write
        2. 7.5.4.2 Combined Format: Read
        3. 7.5.4.3 Stop-Separated Reads
      5. 7.5.5  Supported PMBus Commands
        1. 7.5.5.1 Unsupported PMBus Commands
        2. 7.5.5.2 OPERATION [01h] (R/W Byte)
        3. 7.5.5.3 ON_OFF_CONFIG [02h] (R/W Byte)
        4. 7.5.5.4 WRITE_PROTECT [10h] (R/W Byte)
      6. 7.5.6  CLEAR_FAULTS [03h] (Send Byte)
      7. 7.5.7  STORE_DEFAULT_ALL [11h] (Send Byte)
      8. 7.5.8  RESTORE_DEFAULT_ALL [12h] (Send Byte)
      9. 7.5.9  STATUS_WORD [79h] (Read Word)
      10. 7.5.10 CUSTOM_REG (MFR_SPECIFIC_00) [D0h] (R/W Byte)
      11. 7.5.11 DELAY_CONTROL (MFR_SPECIFIC_01) [D1h] (R/W Byte)
      12. 7.5.12 MODE_SOFT_START_CONFIG (MFR_SPECIFIC_02) [D2h] (R/W Byte)
      13. 7.5.13 FREQUENCY_CONFIG (MFR_SPECIFIC_03) [D3h] (R/W Byte)
      14. 7.5.14 VOUT_ADJUSTMENT (MFR_SPECIFIC_04) [D4h] (R/W Byte)
      15. 7.5.15 Output Voltage Fine Adjustment Soft Slew Rate
      16. 7.5.16 VOUT_MARGIN (MFR_SPECIFIC_05) [D5h] (R/W Byte)
      17. 7.5.17 Output Voltage Margin Adjustment Soft-Slew Rate
      18. 7.5.18 UVLO_THRESHOLD (MFR_SPECIFIC_06) [D6h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Choose the Switching Frequency
        2. 8.2.2.2 Choose the Operation Mode
        3. 8.2.2.3 Choose the Inductor
        4. 8.2.2.4 Choose the Output Capacitor
        5. 8.2.2.5 Determine the Value of R1 and R2
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage range(2) EN –0.3 7.7 V
SW DC –3 25
Transient < 10 ns –5 27
VBST –0.3 31
VBST(3) –0.3 6
VBST when transient < 10 ns 33
VDD –0.3 28
VIN –0.3 25
ADDR, SDA, SCL, FB, MODE, VO –0.3 6
Output voltage range PGOOD –0.3 7.7 V
ALERT TRIP, VREG –0.3 6
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) Voltage values are with respect to the SW terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Input voltage range EN –0.1 7 V
SW –3 20
VBST –0.1 25.5
VBST(1) –0.1 5.5
VDD 4.5 25
VIN 1.5 20
ADDR, SDA, SCL, FB, MODE, VO –0.1 5.5
Output voltage range PGOOD –0.1 7 V
ALERT TRIP, VREG –0.1 5.5
Ambient temperature, TA –40 125 °C
(1) Voltage values are with respect to the SW pin.

6.4 Electrical Characteristics

over operating free-air temperature range, VDD = 12V, VREG = 5 V, VEN = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IVDD VDD bias current TA = 25°C, No load
Power conversion enabled (no switching)		 1350 1850 µA
IVDDSTBY VDD standby current TA = 25°C, No load
Power conversion disabled		 850 1150 µA
IVIN(leak) VIN leakage current TA = 25°C, VEN = 0 V 0.5 µA
VREF OUTPUT
VVREF Reference voltage FB w/r/t GND, TA = 25°C 597 600 603 mV
VVREFTOL Reference voltage tolerance FB w/r/t GND, -40°C ≤ TJ ≤ 85°C –0.5 0.5 %
FB w/r/t GND, –40°C ≤ TJ ≤ 125°C –1.0 1.0
OUTPUT VOLTAGE
IFB FB input current VFB = 600 mV 50 100 nA
IVODIS VO discharge current VVO = 0.5 V, Power Conversion Disabled 6 uA
INTERNAL DAC REFERENCE
VDACTOL1 DAC voltage tolerance 1 FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with certain VOUT_ADJUSTMENT settings only (2) –6.0 6.0 mV
VDACTOL2 DAC voltage tolerance 2 FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with certain VOUT_MARGIN settings only (3) –6.0 6.0 mV
VDACTOL3 DAC voltage tolerance 3 FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with VOUT_ADJUSTMENT=0Dh and VOUT_MARGIN=70h for 5% –6.0 6.0 mV
VDACTOL4 DAC voltage tolerance 4 FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with VOUT_ADJUSTMENT=13h and VOUT_MARGIN=07h for -5% –6.0 6.0 mV
SMPS FREQUENCY
fSW VO switching frequency VIN = 12 V, VVO = 3.3 V, FS<2:0> = 000 250 kHz
VIN = 12 V, VVO = 3.3 V, FS<2:0> = 001 300
VIN = 12 V, VVO = 3.3 V, FS<2:0> = 010 400
VIN = 12 V, VVO = 3.3 V, FS<2:0> = 011 500
VIN = 12 V, VVO = 3.3 V, FS<2:0> = 100 600
VIN = 12 V, VVO = 3.3 V, FS<2:0> = 101 750
VIN = 12 V, VVO = 3.3 V, FS<2:0> = 110 850
VIN = 12 V, VVO = 3.3 V, FS<2:0> = 111 1000
tON(min) Minimum on-time TA = 25°C(1) 60 ns
tOFF(min) Minimum off-time TA = 25°C 175 240 310 ns
INTERNAL BOOTSTRAP SW
VF Forward Voltage VVREG–VBST, TA = 25°C, IF = 10 mA 0.15 0.25 V
IVBST VBST leakage current TA = 25°C, VVBST = 33 V, VSW = 28 V 0.01 1.5 µA
LOGIC THRESHOLD
VENH EN enable threshold voltage 1.3 1.4 1.5 V
VENL EN disable threshold voltage 1.1 1.2 1.3 V
VENHYST EN hysteresis voltage 0.22 V
VENLEAK EN input leakage current –1 0 1 µA
SOFT-START
tSS Soft-start time SST <1:0> = 00 1 ms
SST <1:0> = 01 2
SST <1:0> = 10 4
SST <1:0> = 11 8
POWERGOOD COMPARATOR
VPGTH PGOOD threshold PGOOD in from higher 104 108 111 %
PGOOD in from lower 89 92 96 %
PGOOD out to higher 113 116 120 %
PGOOD out to lower 80 84 87 %
tPGDLY PGOOD delay time Delay for PGOOD going in PGD<2:0>=000 165 256 320 μs
Delay for PGOOD going in PGD<2:0>=001 409 512 614 μs
Delay for PGOOD going in PGD<2:0>=010 0.819 1.024 1.228 ms
Delay for PGOOD going in PGD<2:0>=011 1.638 2.048 2.458 ms
Delay for PGOOD going in PGD<2:0>=100 3.276 4.096 4.915 ms
Delay for PGOOD going in PGD<2:0>=101 6.553 8.192 9.83 ms
Delay for PGOOD going in PGD<2:0>=110 13.104 16.38 19.656 ms
Delay for PGOOD going in PGD<2:0>=111 105 131 157 ms
Delay tolerance for PGOOD coming out 2 µs
IPG PGOOD sink current VPGOOD = 0.5 V 4 6 mA
IPGLK PGOOD leakage current VPGOOD = 5.0 V –1 0 1 µA
POWER-ON DELAY
tPODLY Power-on delay time Delay from enable to switching POD<2:0>=000 356 µs
Delay from enable to switching POD<2:0>=001 612 µs
Delay from enable to switching POD<2:0>=010 1.124 ms
Delay from enable to switching POD<2:0>=011 2.148 ms
Delay from enable to switching POD<2:0>=100 4.196 ms
Delay from enable to switching POD<2:0>=101 8.292 ms
Delay from enable to switching POD<2:0>=110 16.48 ms
Delay from enable to switching POD<2:0>=111 32.86 ms
CURRENT DETECTION
IOCL Current limit threshold, valley RTRIP = 49 kΩ 11.5 15.0 17.5 A
RTRIP = 28 kΩ 6.5 8 11
IOCLN Negative current limit threshold, valley RTRIP = 49 kΩ -18.0 –14.9 -10.5 A
RTRIP = 28 kΩ -11.5 -8.0 -6.0
VZC Zero cross detection offset 0 mV
PROTECTIONS
VVREGUVLO VREG undervoltage-lockout (UVLO) threshold voltage Wake-up 3.25 3.34 3.41 V
Shutdown 3.00 3.12 3.19
VVDDUVLO VDD UVLO threshold voltage Wake-up (default) 4.15 4.25 4.35 V
Shutdown 3.95 4.05 4.15
VOVP Overvoltage-protection (OVP) threshold voltage OVP detect voltage 116 120 124 %
tOVPDLY OVP propagation delay With 100-mV overdrive 300 ns
VUVP Undervoltage-protection (UVP) threshold voltage UVP detect voltage 64 68 71 %
tUVPDLY UVP delay UVP filter delay 1 ms
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold(1) Shutdown temperature 140 °C
Hysteresis 40
LDO VOLTAGE
VREG LDO output voltage VIN = 12 V, ILOAD = 10 mA 4.65 5 5.45 V
VDOVREG LDO low droop drop-out voltage VIN = 4.5 V, ILOAD = 30 mA, TA = 25°C 365 mV
ILDOMAX LDO over-current limit VIN = 12 V, TA = 25°C 170 200 mA
INTERNAL MOSFETS
RDS(on)H High-side MOSFET on-resistance TA = 25°C 9.9 11.4 mΩ
RDS(on)L Low-side MOSFET on-resistance TA = 25°C 4.3 4.94 mΩ
PMBus SCL and SDA INPUT BUFFER LOGIC THRESHOLDS
VIL-PMBUS SCL and SDA low-level input voltage(1) 0°C ≤ TJ ≤ 85°C 0.8 V
VIH-PMBUS SCL and SDA high-level input voltage(1) 0°C ≤ TJ ≤ 85°C 2.1 V
VHY-PMBUS SCL and SDA hysteresis voltage(1) 0°C ≤ TJ ≤ 85°C 240 mV
PMBus SDA and ALERT OUTPUT PULLDOWN
VOL1-PMBUS SDA and ALERT low-level output voltage(1) VDDPMBus = 5.5 V, RPULLUP = 1.1 kΩ,
0°C ≤ TJ ≤ 85°C		 0.4 V
VOL2-PMBUS SDA and ALERT low-level output voltage(1) VDDPMBus = 3.6 V, RPULLUP = 0.7 kΩ,
0°C ≤ TJ ≤ 85°C		 0.4 V
(1) Specified by design. Not production tested.
(2) Tested at these VOUT_ADJUSTMENT settings: –9.0%, –8.25%, –5.25%, –2.25%, 0.0%, 3.00%, 6.00%, 9.0%
(3) Tested at these VOUT_MARGIN settings: –11.62%, –10.74%, –7.06%, –3.15%, 0%, 3.7%, 7.74%, 12.05%

6.5 Thermal Information

THERMAL METRIC(1) TPS549A20 UNIT
RVE
(VQFN-CLIP)
28 PINS
θJA Junction-to-ambient thermal resistance 37.5 °C/W
θJCtop Junction-to-case (top) thermal resistance 34.1 °C/W
θJB Junction-to-board thermal resistance 18.1 °C/W
ψJT Junction-to-top characterization parameter 1.8 °C/W
ψJB Junction-to-board characterization parameter 18.1 °C/W
θJCbot Junction-to-case (bottom) thermal resistance 2.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

6.6 Typical Characteristics

TA = 25°C (unless otherwise noted)
TPS549A20 D001_SLUSC78.gif
fSW = 500 kHz Auto-skip Mode
VIN = 12 V
Figure 1. Efficiency vs. Output Current
TPS549A20 D003_SLUSC78.gif
fSW = 970 kHz Auto-skip Mode
VIN = 12 V
Figure 3. Efficiency vs. Output Current
TPS549A20 D005_SLUSC78.gif
fSW = 500 kHz VOUT = 1.2 V
Figure 5. DC Load Regulation
TPS549A20 D007_SLUSC78.gif
fSW = 500 kHz VOUT = 1.2 V
Figure 7. DC Load Regulation
TPS549A20 D051_SLUSC78.gif
fSW = 500 kHz VIN = 12 V
VOUT = 5 V
Figure 9. Safe Operating Area
TPS549A20 fsw_mode_perf_slusc78.gif
VIN = 12 V VOUT = 1.2 V
Figure 11. Switching Frequency vs. Output Current
TPS549A20 D002_SLUSC78.gif
fSW = 500 kHz FCCM
VIN = 12 V
Figure 2. Efficiency vs. Output Current
TPS549A20 D004_SLUSC78.gif
fSW = 970 kHz FCCM
VIN = 12 V
Figure 4. Efficiency vs. Output Current
TPS549A20 D006_SLUSC78.gif
fSW = 970 kHz VOUT = 1.2 V
Figure 6. DC Load Regulation
TPS549A20 D008_SLUSC78.gif
fSW = 970 kHz VOUT = 1.2 V
Figure 8. DC Load Regulation
TPS549A20 D052_SLUSC78.gif
fSW = 500 kHz VIN = 12 V
VOUT = 1 V
Figure 10. Safe Operating Area
TPS549A20 waveform_01_slusc78.png
fSW = 1 MHz VIN = 12 V
VOUT = 1.2 V ILOAD = 0 A
Figure 12. Skip Mode Steady-State Operation
TPS549A20 waveform_03_slusc78.png
fSW = 1 MHz VIN = 12 V
VOUT = 1.2 V ILOAD = 0.1 A
Figure 14. Skip Mode Steady-State Operation
TPS549A20 waveform_05_slusc78.png
fSW = 1 MHz VIN = 12 V
VOUT = 1.2 V ILOAD = 8 A
Figure 16. Skip Mode Steady-State Operation
TPS549A20 waveform_07_slusc78.png
ILOAD from 0 A to 8 A Div = 2 A/µs
VIN = 12 V VOUT = 1.2 V
fSW = 1 MHz
Figure 18. Auto-skip Mode Load Transient
TPS549A20 waveform_09_slusc78.png
fSW = 1 MHz VIN = 12 V
VOUT = 1.2 V
Figure 20. Auto-skip Mode Start-Up
TPS549A20 waveform_11_slusc78.png
ILOAD = 0 A VIN = 12 V
VOUT = 1.2 V fSW = 1 MHz
Figure 22. Skip Mode Pre-Bias Start-Up
TPS549A20 waveform_13_slusc78.png
ILOAD = 8A VIN = 12 V
VOUT = 1.2 V fSW = 1 MHz
Figure 24. Auto-skip Mode Shutdown Operation
TPS549A20 waveform_15_slusc78.png
ILOAD = 0 A VIN = 12 V
VOUT = 1.2 V fSW = 1 MHz
Figure 26. FCCM Shutdown Operation
TPS549A20 waveform_02_slusc78.png
fSW = 1 MHz VIN = 12 V
VOUT = 1.2 V ILOAD = 0 A
Figure 13. FCCM Steady-State Operation
TPS549A20 waveform_04_slusc78.png
fSW = 1 MHz VIN = 12 V
VOUT = 1.2 V ILOAD = 0.1 A
Figure 15. Steady-State Operation
TPS549A20 waveform_06_slusc78.png
fSW = 1 MHz VIN = 12 V
VOUT = 1.2 V ILOAD = 8 A
Figure 17. Skip Mode Steady-State Operation
TPS549A20 waveform_08_slusc78.png
ILOAD from 0 A to 8 A Div = 2 A/µs
VIN = 12 V VOUT = 1.2 V
fSW = 1 MHz
Figure 19. Load Transient
TPS549A20 waveform_10_slusc78.png
fSW = 1 MHz VIN = 12 V
VOUT = 1.2 V
Figure 21. FCCM Mode Start-Up
TPS549A20 waveform_12_slusc78.png
ILOAD = 0 A VIN = 12 V
VOUT = 1.2 V fSW = 1 MHz
Figure 23. FCCM Pre-Bias Start-Up
TPS549A20 waveform_14_slusc78.png
ILOAD = 8 A VIN = 12 V
VOUT = 1.2 V fSW = 1 MHz
Figure 25. Auto-skip Mode Shutdown Operation
TPS549A20 waveform_16_slusc78.png
ILOAD = 8 A VIN = 12 V
VOUT = 1.2 V fSW = 1 MHz
Figure 27. FCCM Shutdown Operation
TPS549A20 waveform_17_slusc78.png Figure 28. Overcurrent Protection Hiccup
TPS549A20 waveform_18_slusc78.png Figure 29. Overcurrent Protection

6.7 Thermal Performance

fSW = 500 kHz, VIN = 12 V, VOUT = 5 V, IOUT = 12 A, COUT = 10 × 22 µF (1206, 6.3 V, X5R), RBOOT = 0 Ω, SNB = 3 Ω + 470 pF Inductor: LOUT = 1 µH, PCMC135T-1R0MF, 12.6 mm × 13.8 mm × 5 mm, 2.1 mΩ (typ)
TPS549A20 themal_photo_slusc78.gif Figure 30. SP1: 68.2℃ ( TPS549A20 ), SP2: 75℃ (Inductor)