SNVSAU8 Data sheet

SNVSAU8A June 2017 – February 2024 TPS549B22

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

RVF|40

Thermal pad, mechanical data (Package|Pins)

RVF|40
- QFND333E

Orderable Information

5.5 Electrical Characteristics

over operating free-air temperature range, V_VDD = 12 V, V_{EN_UVLO} = 5 V (unless otherwise noted)

PARAMETER		TEST CONDITION		MIN	TYP	MAX	UNIT
MOSFET ON-RESISTANCE (R_DS(on))
R_DS(on)	High-side FET	(V_BOOT – V_SW) = 5 V, I_D = 25 A, T_J = 25°C			4.1		mΩ
R_DS(on)	Low-side FET	V_VDD = 5 V, I_D = 25 A, T_J = 25°C			1.9		mΩ
INPUT SUPPLY AND CURRENT
V_VDD	VDD supply voltage	Nominal VDD voltage range		4.5		22	V
I_VDD	VDD bias current	No load, power conversion enabled (no switching), T_A = 25°C,			2		mA
I_VDDSTBY	VDD standby current	No load, power conversion disabled, T_A = 25°C			700		µA
UNDERVOLTAGE LOCKOUT
V_{VDD_UVLO}	VDD UVLO rising threshold			4.123	4.25	4.41	V
V_{VDD_UVLO(HYS)}	VDD UVLO hysteresis				0.2		V
V_{EN_ON_TH}	EN_UVLO on threshold			1.45	1.6	1.75	V
V_{EN_HYS}	EN_UVLO hysteresis			270	300	340	mV
I_{EN_LKG}	EN_UVLO input leakage current	V_{EN_UVLO} = 5 V		–1	0	1	µA
INTERNAL REFERENCE VOLTAGE RANGE
V_INTREF	Internal REF voltage				900.4		mV
V_INTREFTOL	Internal REF voltage tolerance	–40°C ≤ T_J ≤ 125°C		–0.5%		0.5%
V_INTREF	Internal REF voltage range			0.6		1.2	V
OUTPUT VOLTAGE
V_{IOS_LPCMP}	Loop comparator input offset voltage⁽¹⁾			–2.5		2.5	mV
I_RSP	RSP input current	V_RSP = 600 mV		–1		1	µA
I_VO(dis)	VO discharge current	V_VO = 0.5 V, power conversion disabled		8	12		mA
DIFFERENTIAL REMOTE SENSE AMPLIFIER
f_UGBW	Unity gain bandwidth⁽¹⁾			5	7		MHz
A₀	Open loop gain⁽¹⁾			75			dB
SR	Slew rate⁽¹⁾				±4.7		V/µsec
V_IRNG	Input range⁽¹⁾			–0.2		1.8	V
V_OFFSET	Input offset voltage⁽¹⁾			–3.5		3.5	mV
INTERNAL BOOT STRAP SWITCH
V_F	Forward voltage	V_BP-BOOT, I_F = 10 mA, T_A = 25°C			0.1	0.2	V
I_BOOT	VBST leakage current	V_BOOT = 30 V, V_SW = 25 V, T_A = 25°C			0.01	1.5	µA
SWITCHING FREQUENCY
f_SW	VO switching frequency⁽²⁾	V_IN = 12 V, V_VO = 1 V, T_A = 25°C		275	315	350	kHz
				380	425	475
				490	550	615
				585	650	740
				740	825	930
				790	900	995
				920	1025	1160
				950	1125	1250
t_ON(min)	Minimum on-time⁽¹⁾				60		ns
t_OFF(min)	Minimum off-time⁽¹⁾	DRVH falling to rising				300	ns
MODE, VSEL, ADDR DETECTION
V_{DETECT_TH}	MODE, VSEL, and ADDR detection voltage	V_BP = 2.93 V, R_HIGH = 100 kΩ	Open		V_BP		V
			R_LOW = 187 kΩ		1.9091
			R_LOW = 165 kΩ		1.8243
			R_LOW = 147 kΩ		1.7438
			R_LOW = 133 kΩ		1.6725
			R_LOW = 121 kΩ		1.6042
			R_LOW = 110 kΩ		1.5348
			R_LOW = 100 kΩ		1.465
			R_LOW = 90.9 kΩ		1.3952
			R_LOW = 82.5 kΩ		1.3245
			R_LOW = 75 kΩ		1.2557
			R_LOW = 68.1 kΩ		1.187
			R_LOW = 60.4 kΩ		1.1033
			R_LOW = 53.6 kΩ		1.0224
			R_LOW = 47.5 kΩ		0.9436
			R_LOW = 42.2 kΩ		0.8695
			R_LOW = 37.4 kΩ		0.7975
			R_LOW = 33.2 kΩ		0.7303
			R_LOW = 29.4 kΩ		0.6657
			R_LOW = 25.5 kΩ		0.5953
			R_LOW = 22.1 kΩ		0.5303
			R_LOW = 19.1 kΩ		0.4699
			R_LOW = 16.5 kΩ		0.415
			R_LOW = 14.3 kΩ		0.3666
			R_LOW = 12.1 kΩ		0.3163
			R_LOW = 10 kΩ		0.2664
			R_LOW = 7.87 kΩ		0.2138
			R_LOW = 6.19 kΩ		0.1708
			R_LOW = 4.64 kΩ		0.1299
			R_LOW = 3.16 kΩ		0.0898
			R_LOW = 1.78 kΩ		0.0512
			R_LOW = 0 Ω		GND
SOFT-START
t_SS	Soft-start time	V_OUT rising from 0 V to 95% of final set point, R_{MODE_HIGH} = 100 kΩ	R_{MODE_LOW} = 60.4 kΩ	7	8⁽⁴⁾	10	ms
			R_{MODE_LOW} = 53.6 kΩ	3.6	4⁽⁵⁾	5.2
			R_{MODE_LOW} = 47.5 kΩ	1.6	2	2.8
			R_{MODE_LOW} = 42.2 kΩ	0.8	1	1.6
POWER-ON DELAY
t_PODLY	Power-on delay time	Delay from enable to switching POD[2:0] = 000			256		µs
		Delay from enable to switching POD[2:0] = 001			512		µs
		Delay from enable to switching POD[2:0] = 010			1.024		ms
		Delay from enable to switching POD[2:0] = 011			2.048
		Delay from enable to switching POD[2:0] = 100			4.096
		Delay from enable to switching POD[2:0] = 101			8.192
		Delay from enable to switching POD[2:0] = 110			16.384
		Delay from enable to switching POD[2:0] = 111			32.768
PGOOD COMPARATOR
V_PGTH	PGOOD threshold	PGOOD in from higher		105	108	111	%V_REF
		PGOOD in from lower		89	92	95
		PGOOD out to higher			120
		PGOOD out to lower			68
I_PG	PGOOD sink current	V_PGOOD = 0.5 V			6.9		mA
t_PGDLY	PGOOD delay time	Delay for PGOOD going in, PGD[2:0] = 000			256		µs
		Delay for PGOOD going in, PGD[2:0] = 001			512		µs
		Delay for PGOOD going in, PGD[2:0] = 010			1.024		ms
		Delay for PGOOD going in, PGD[2:0] = 011			2.048
		Delay for PGOOD going in, PGD[2:0] = 100			4.096
		Delay for PGOOD going in, PGD[2:0] = 101			8.192
		Delay for PGOOD going in, PGD[2:0] = 110			16.384
		Delay for PGOOD going in, PGD[2:0] = 111			131
		Delay for PGOOD coming out				2	µs
I_PGLK	PGOOD leakage current	V_PGOOD = 5 V		–1	0	1	μA
CURRENT DETECTION
I_{OCL_VA}	Valley current limit threshold	R_LIM = 61.9 kΩ			30		A
		OC tolerance			±15%⁽³⁾
		R_LIM = 51.1 kΩ			25		A
		OC tolerance			±15%⁽³⁾
		R_LIM = 40.2 kΩ		17	20	23	A
I_{OCL_VA_N}	Negative valley current limit threshold	R_LIM = 61.9 kΩ			–30		A
		R_LIM = 51.1 kΩ			–25		A
		R_LIM = 40.2 kΩ			–20
I_{CLMP_LO}	Clamp current at V_LIM clamp at lowest	V_{ILIM_CLMP} = 0.1 V, T_A = 25°C			5		A
I_{CLMP_HI}	Clamp current at V_LIM clamp at highest	V_{ILIM_CLMP} = 1.2 V, T_A = 25°C			50		A
PROTECTIONS AND OOB
V_BPUVLO	BP UVLO threshold voltage	Wake-up			3.32		V
V_BPUVLO	BP UVLO threshold voltage	Shutdown			3.11
V_OVP	OVP threshold voltage	OVP detect voltage		117%	120%	123%	V_REF
t_OVPDLY	OVP response time	100-mV over drive				1	µs
V_UVP	UVP threshold voltage	UVP detect voltage		65%	68%	71%	V_REF
t_UVPDLY	UVP delay filter delay time				1		ms
V_OOB	OOB threshold voltage				8%		V_REF
t_HICDLY	Hiccup blanking time	t_SS = 1 ms			16		ms
		t_SS = 2 ms			24		ms
		t_SS = 4 ms			38		ms
		t_SS = 8 ms			67		ms
BP VOLTAGE
V_BP	BP LDO output voltage	V_IN = 12 V, 0 A ≤ I_LOAD ≤ 10 mA,			5.07		V
V_BPDO	BP LDO dropout voltage	V_IN = 4.5 V, I_LOAD = 30 mA, T_A = 25°C				365	mV
I_BPMAX	BP LDO overcurrent limit	V_IN = 12 V, T_A = 25°C			100		mA
PMB_CLK and PMB_DATA INPUT BUFFER LOGIC THRESHOLDS
V_IL-PMBUS	PMB_CLK and PMB_DATA low-level input voltage⁽¹⁾					0.8	V
V_IH-PMBUS	PMB_CLK and PMB_DATA high-level input voltage⁽¹⁾			1.35			V
V_HY-PMBUS	PMB_CLK and PMB_DATA hysteresis voltage⁽¹⁾				150		mV
PMB_CLK and SMB_ALRT OUTPUT PULLDOWN
V_OL-PMBUS	PMB_DATA and SMB_ALRT low-level output voltage⁽¹⁾	I_SINK = 20 mA				0.4	V
THERMAL SHUTDOWN
T_SDN	Built-In thermal shutdown threshold⁽¹⁾	Shutdown temperature		155	165		°C
T_SDN	Built-In thermal shutdown threshold⁽¹⁾	Hysteresis				30	°C