7.3.7.1 Current Limit (ILIM) Functionality

Figure 26. Current Limit Resistance vs OCP Valley Overcurrent Limit

The ILIM pin sets the OCP level. Connect the ILIM pin to GND through the voltage setting resistor, R_ILIM. In order to provide both good accuracy and cost effective solution, TPS549D22 device supports temperature compensated internal MOSFET R_DS(on) sensing.

Also, the TPS549D22 device performs both positive and negative inductor current limiting with the same magnitudes. The positive current limit normally protects the inductor from saturation that causes damage to the high-side FET and low-side FET. The negative current limit protects the low-side FET during OVP discharge.

The voltage between GND pin and SW pin during the OFF time monitors the inductor current. The current limit has 3000 ppm/°C temperature slope to compensate the temperature dependency of the on-resistance (R_DS(on)). The GND pin is used as the positive current sensing node.

TPS549D22 device uses cycle-by-cycle over-current limiting control. The inductor current is monitored during the OFF state and the controller maintains the OFF state during the period that the inductor current is larger than the overcurrent ILIM level. V_ILIM sets the valley level of the inductor current.

7.3.7.2 VDD Undervoltage Lockout (UVLO)

The TPS549D22 device has an UVLO protection function for the VDD supply input. The on-threshold voltage is 4.25 V with 200 mV of hysteresis. During a UVLO condition, the device is disabled regardless of the EN_UVLO pin voltage. The supply voltage (V_VDD) must be above the on-threshold to begin the pin strap detection.

7.3.7.3 Overvoltage Protection (OVP) and Undervoltage Protection (UVP)

The device monitors a feedback voltage to detect overvoltage and undervoltage. When the feedback voltage becomes lower than 68% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 1 ms, the device latches OFF both high-side and low-side MOSFETs drivers. The UVP function enables after soft-start is complete.

When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side FET is turned on again for a minimum on-time. The TPS549D22 device operates in this cycle until the output voltage is pulled down under the UVP threshold voltage for 1 ms. After the 1-ms UVP delay time, the high-side FET is latched off and low-side FET is latched on. The fault is cleared with a reset of VDD or by retoggling the EN pin.

7.3.7.4 Out-of-Bounds Operation

The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, so the device is not latched off after an OOB event. OOB protection operates as an early no-fault overvoltage-protection mechanism. During the OOB operation, the controller operates in forced PWM mode only by turning on the low-side FET. Turning on the low-side FET beyond the zero inductor current quickly discharges the output capacitor thus causing the output voltage to fall quickly toward the setpoint. During the operation, the cycle-by-cycle negative current limit is also activated to ensure the safe operation of the internal FETs.

7.3.7.5 Overtemperature Protection

TPS549D22 device has overtemperature protection (OTP) by monitoring the die temperature. If the temperature exceeds the threshold value (default value 165°C), TPS549D22 device is shut off. When the temperature falls about 25°C below the threshold value, the device turns on again. The OTP is a non-latch protection.

7.5.1.1 Address Selection (ADDR) Pin

The TPS549D22 allows up to 16 different chip addresses for PMBus communication with the first 3 bits fixed as 001. The address selection process is defined by resistor divider ratio from BP pin to ADDR pin, and the address detection circuit will start to work only after the initial power up when VDD has risen above its UVLO threshold. lists all combinations of the address selections. The 1% or better tolerance resistors with typical temperature coefficient of ±100ppm/°C are recommended.

ADDR pin strap configuration also programs the light load conduction mode.

7.5.1.2 VSEL Pin

VSEL pin strap configuration is used to program initial boot voltage value, hiccup mode and latch off mode. The initial boot voltage is used to program the main loop voltage reference point. VSEL voltage settings provide TI designated discrete internal reference voltages. Table 2 lists internal reference voltage selections.

7.5.1.3 DCAP3 Control and Mode Selection

The MODE pinstrap configuration programs the control topology and internal soft-start timing selections. The TPS549D22 device supports both DCAP3 and DCAP operation

MODE[4] selection bit is used to set the control topology. If MODE[4] bit is “0”, it selects DCAP operation. If MODE[4] bit is “1”, it selects DCAP3 operation.

MODE[1] and MODE[0] selection bits are used to set the internal soft-start timing

7.5.1.4 Application Workaround to Support 4-ms and 8-ms SS Settings

In order to properly design for 4-ms and 8-ms SS settings, additional application consideration is needed. The recommended application workaround to support the 4-ms and 8-ms soft-start settings is to ensure sufficient time delay between the VDD and EN_UVLO signals. The minimum delay between the rising maximum VDD_UVLO level and the minimum turnon threshold of EN_UVLO is at least T_{DELAY_MIN}.

For example, if SS setting is 4 ms and V_REF = 1 V, program the minimum delay at least 9 ms; if SS setting is 8 ms, the minimum delay should be programmed at least 18 ms. See Figure 27 and Figure 28 for detailed timing requirement. Because TPS549D22 is a PMBus device, the end user has the option of programming power-on delay (POD) as another workaround. Be sure to follow the same calculation to determine the required POD (see MFR_SPECIFIC_01 (address = D1h) and Table 25 for more information).

Figure 27. Proper Sequencing of V_DD and EN_UVLO to Support the Use of 4-ms SS Setting

Figure 28. Minimum Delay Between V_DD and EN_UVLO to Support the Use of 4-ms and 8-ms SS settings

The workaround/consideration described previously is not required for SS settings of 1 ms and 2 ms.

7.5.2.1 RSP/RSN Remote Sensing Functionality

RSP and RSN pins are used for remote sensing purpose. In the case where feedback resistors are required for output voltage programming, the RSP pin should be connected to the mid-point of the resistor divider and the RSN pin should always be connected to the load return. In the case where feedback resistors are not required as when the VSEL programs the output voltage set point, the RSP pin should be connected to the positive sensing point of the load and the RSN pin should always be connected to the load return.

RSP and RSN pins are extremely high-impedance input terminals of the true differential remote sense amplifier. The feedback resistor divider should use resistor values much less than 100 kΩ.

7.5.2.1.1 Output Differential Remote Sensing Amplifier

The examples in this section show simplified remote sensing circuitry where each example uses an internal reference of 1 V. Figure 29 shows remote sensing without feedback resistors, with an output voltage set point of 1 V. Figure 30 shows remote sensing using feedback resistors, with an output voltage set point of 5 V.

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Figure 29. Remote Sensing Without Feedback Resistors

Figure 30. Remote Sensing With Feedback Resistors

7.5.2.2 Power Good (PGOOD Pin) Functionality

The TPS549D22 device has power-good output that registers high when switcher output is within the target. The power-good function is activated after soft-start has finished. When the soft-start ramp reaches 300 mV above the internal reference voltage, SSend signal goes high to enable the PGOOD detection function. If the output voltage becomes within ±8% of the target value, internal comparators detect power-good state and the power good signal becomes high after a 1-ms programmable delay. If the output voltage goes outside of ±16% of the target value, the power good signal becomes low after two microsecond (2-µs) internal delay. The open-drain power-good output must be pulled up externally. The internal N-channel MOSFET does not pull down until the VDD supply is above 1.2 V.

7.5.3.1 TPS549D22 Limitations to the PMBUS Specifications

TPS549D22 only recognizes seven bit addressing. This means TPS549D22 is not compatible with ten bit addressing and CBUS communication. The device can operate in standard mode (100 kbit/s), fast mode (400 kbit/s) or faster mode (1000 kbit/s).

7.5.3.2 Slave Address Assignment

The seven bit slave address is 001A₃A₂A₁A₀x, where A₃A₂A₁A₀ is set by the ADDR pin on the device. Bit 0 is the data direction bit, i.e. 001A₃A₂A₁A₀0 is used for write operation and 001A₃A₂A₁A₀1 is used for read operation.

7.5.3.3 PMBUS Address Selection

TPS549D22 allows up to 16 different chip addresses for PMBus communication, with the first three bits fixed as 001. The address selection process is defined by the resistor divider ratio from BP pin to ADDR pin, and the address detection circuit will start to work only after VDD input supply has risen above its UVLO threshold. Table 4 lists the divider ratio and some example resistor values. The 1% tolerance resistors with typical temperature coefficient of ±100 ppm/ºC are recommended. Higher performance resistors can be used if tighter noise margin is required for more reliable address detection.

7.5.3.4 Supported Formats

The supported formats are described in the following subsections.

7.5.3.5 Stop Separated Reads

Stop-separated reads can also be used. This format allows a master to set up the register address pointer for a read and return to that slave at a later time to read the data. In this format the slave chip address followed by a write bit are sent after a start [S] condition. TPS549D22 then acknowledges it is being addressed, and the master responds with the 8-bit register address byte. The master then sends a stop or restart condition and may then address another slave. After performing other tasks, the master can send a start or restart condition to the TPS549D22 with a read command. The device acknowledges this request and returns the data from the register location that had been set up previously.

7.5.3.6 Supported PMBUS Commands and Registers

Only the following PMBus commands are supported by TPS549D22, and not all parts of each command are supported.

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Figure 31. Startup and VOUT_COMMAND Timing Diagram

7.5.4.1 OPERATION Register (address = 1h)

7.5.4.2 ON_OFF_CONFIG Register (address = 2h)

7.5.4.3 CLEAR FAULTS (address = 3h)

The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command simultaneously clears all bits in all status registers. At the same time, the device clears its SMB_ALERT# signal output if the device is asserting the SMB_ALERT# signal.

The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. If the fault is still present when the bit is cleared, the fault bit shall immediately be set again and the host notified by the usual means.

7.5.4.4 WRITE PROTECT (address = 10h)

7.5.4.5 STORE_DEFAULT_ALL (address = 11h)

Store all of the current storable register settings in the EEPROM memory as the new defaults on power up.

It is permitted to use the STORE_DEFAULT_ALL command while the device is operating. However, the device may be unresponsive during the write operation with unpredictable memory storage results. TI recommends to turn the device output off before issuing this command.

EEPROM programming faults will set the ‘CML’ bit in the STATUS_BYTE and the ‘MEM’ bit in the STATUS_CML registers.

7.5.4.6 RESTORE_DEFAULT_ALL (address = 12h)

Write EEPROM data to those CSRs that: (1) have EEPROM support, and; (2) are unprotected according to current setting of WRITE_PROTECT.

It is permitted to use the RESTORE_DEFAULT_ALL command while the device is operating. However, the device may be unresponsive during the copy operation with unpredictable, undesirable or even catastrophic results. TI recommends to turn the device output off before issuing this command.

No data bytes are sent, just the command code is sent.

7.5.4.7 CAPABILITY (address = 19h)

This command provides a way for a host system to determine some key capabilities of this PMBus device.

7.5.4.8 VOUT_MODE (address = 20h)

7.5.4.9 VOUT_COMMAND (address = 21h)

The VOUT_COMMAND command sets the output voltage in volts. The exponent is set be VOUT_MODE at –9 (equivalent of 1.9531 mV/LSB). The programmed V_OUT is computed as:

The support range for TPS549D22 is: 0.5996 V to 1.1992 V. It is effectively 9-bits limited to 307 to 614 decimal. Slew rate control is provided through MODE pin.

V_OUT setps 1 step/t_slew, where t_slew is programmable by MODE pin: 4, 8, 16, or 32 µs.

7.5.4.10 VOUT_MARGIN_HIGH (address = 25h)

The VOUT_MARGIN_HIGH command loads the TPS549D22 with the voltage to which the output is to be changed when the OPERATION command is set to “Margin High”.

The data bytes are two bytes formatted according to the setting of the VOUT_MODE command.

The support margin range for TPS549D22 is: 0.5996 V to 1.1992 V. It is effectively 9-bits limited to 307 to 614 decimal. Slew rate control is provided through MODE pin.

7.5.4.11 VOUT_MARGIN_LOW (address = 26h)

The VOUT_MARGIN_LOW command loads the TPS549D22 with the voltage to which the output is to be changed when the OPERATION command is set to “Margin Low”.

The data bytes are two bytes formatted according to the setting of the VOUT_MODE command.

The support margin range for TPS549D22 is: 0.5996 V to 1.1992 V. It is effectively 9-bits limited to 307 to 614 decimal. Slew rate control is provided through MODE pin.

7.5.4.12 STATUS_BYTE (address = 78h)

7.5.4.13 STATUS_WORD (High Byte) (address = 79h)

7.5.4.14 STATUS_VOUT (address = 7Ah)

7.5.4.15 STATUS_IOUT (address = 7Bh)

7.5.4.16 STATUS_CML (address = 7Eh)

7.5.4.17 MFR_SPECIFIC_00 (address = D0h)

7.5.4.18 MFR_SPECIFIC_01 (address = D1h)

7.5.4.19 MFR_SPECIFIC_02 (address = D2h)

The MFR_SPECIFIC_02 register allows the user to read the configuration of various pinstrap features and/or overwrite them. Note, that any overwritten values here are only good until the next power-on-reset; when all parameters will revert back to their pinstrap configurations.

7.5.4.20 MFR_SPECIFIC_03 (address = D3h)

The MFR_SPECIFIC_03 register allows the user to read the configuration of the DCAP pinstrap feature (and/or overwrite it); as well configure the Ramp Generator and the PWM switching frequency.

7.5.4.21 MFR_SPECIFIC_04 (address = D4h)

The MFR_SPECIFIC_04 register allows the user to configure the D-CAP offset reduction and fixed offset correction.

7.5.4.22 MFR_SPECIFIC_06 (address = D6h)

The MFR_SPECIFIC_06 is a user-accessible register dedicated for configuring the VDD Under-voltage LockOut threshold.

7.5.4.23 MFR_SPECIFIC_07 (address = D7h)

The MFR_SPECIFIC_07 is a user-accessible register dedicated for configuring the device’s PGOOD threshold and external tracking options.

7.5.4.24 MFR_SPECIFIC_44 (address = FCh)

The DEVICE_CODE command returns a 12-bit unique identifier code for the device and a 4 bit device revision code. Device revisions codes should start at 0x0.