Table 3. Design Parameters

8.2.2.1 Output Voltage

Before beginning design, ensure that the series capacitor buck converter can be used in the application. It is recommended to use this converter when the minimum input voltage is at least five times greater than the target output voltage. If this recommendation is not followed, output voltage dropout can occur at heavy load conditions and poor transient response to load increases can result.

The output voltage is set by connecting a resistor divider network from the output voltage to the FB pin of the device and to AGND. It is recommended that the lower divider resistor maintain a range between 1 kΩ and 10 kΩ. To change the output voltage of a design, it is necessary to select the value of the upper resistor. The value of R_TOP for a specific output voltage can be calculated using Equation 2.

Equation 2.

8.2.2.2 Switching Frequency

A key design step is to decide on a switching frequency for the regulator. There is a tradeoff between higher and lower switching frequencies. Higher switching frequencies may produce a smaller solution size using lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. However, the higher switching frequency creates extra switching loss, which reduces the converter’s efficiency and thermal performance. In this design, a moderate switching frequency of 2 MHz per phase is selected to achieve both a small solution size and a high efficiency operation. Refer to Table 1 for the SS/FSEL programming resistor selection.

8.2.2.3 On-Time

The TON pin requires a resistor to set the nominal on-time and to support the input voltage feedforward circuit. The resistance value used also influences the internal ramp in the controller. As a starting point, Equation 3 is recommended for selecting the TON resistor.

Equation 3.

The R_TON resistor (R5) is calculated to be 21 kΩ. The selected value for this design example is 22.1 kΩ. During startup, the converter uses the nominal on-time programmed through TON. The phase lock loop (PLL) is only activated after startup is complete. When the PLL is engaged, the on-time is adjusted. If the nominal on-time programmed through the TON pin is not close to the on-time when the PLL is engaged, the SYNC range of the device may be reduced. The TON resistor can also be adjusted to tune the controller. Lowering the R_TON value will increase the internal ramp height. This will reduce the converter’s sensitivity to noise and jitter but it will also reduce the transient response capabilities of the converter.

8.2.2.4 Inductor Selection

To calculate the value of the output inductors, use Equation 4. K_IND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. In general, the inductor ripple value is at the discretion of the designer; however, K_IND is normally from 0.1 to 0.4 for the majority of applications.

Equation 4.

For this design example, use K_IND = 0.4 and the inductor value is calculated to be 249 nH. For this design, the nearby standard value of 220 nH was chosen. For the output filter inductor, it is generally recommended that the RMS current and saturation current ratings not be exceeded. The current ripple, RMS, and peak inductor current are calculated in Equation 5, Equation 6, and Equation 7.

Equation 5.

Equation 6.

Equation 7.

For this design, the RMS inductor current is calculated to be 5.04 A and the peak inductor current is 6.13 A. The chosen inductor is 220 nH with a saturation current rating of 8.2 A and a dc current rating of 7.6 A.

The current flowing through each inductor is the inductor ripple current plus half the output current. During power up, faults, or transient load conditions, the inductor current can increase above the peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than half the load current limit rather than the peak inductor current in steady state. Many inductors today have soft saturation characteristics that may be able to ride through a transient that pushes current beyond the saturation rating specified in the datasheet. An example list of inductors that have been tested to work with the TPS54A20 are shown in Table 4. Inductors not listed below can also be used with this device.

8.2.2.5 Output Capacitor Selection

For most applications, the primary consideration for selecting the value of the output capacitor is how the regulator responds to a large change in load current. The output capacitance may also be selected based on output voltage ripple or closed-loop bandwidth design objectives.

The output capacitance required to maintain an output voltage ripple ΔV_OUT during steady-state operation can be estimated using Equation 8.

Equation 8.

The desired response to a large change in the load current is typically the most stringent criteria. The output capacitor needs to supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is also temporarily not able to supply sufficient output current if there is a large, fast change in the load current such as a transition from no load to full load. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The minimum output capacitance required for a load increase can be estimated using Equation 9.

Equation 9.

In low voltage applications, the inductor slew rate during a load step decrease is sometimes slower than its slew rate during a load step increase. The minimum output capacitance required for a load decrease can be estimated using Equation 10 for a given tolerable amount of overshoot in the output voltage.

Equation 10.

Here ΔI_OUT is the change in output current and ΔV_OUT is the allowable change in the output voltage. For this design example, the transient load response is specified as a 3% change in V_OUT for a load step of 5A. For this example, ΔI_OUT = 5 A and ΔV_OUT = 0.03 x 1.2 = 0.036 V. Based on these design parameters, a minimum capacitance of 93 µF is calculated using Equation 9. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which also increases this minimum value. For this design example, two 47 µF, 6.3 V rated, ceramic capacitors with 3 mΩ of ESR are selected.

8.2.2.6 Input Capacitor Selection

The TPS54A20 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 µF of effective capacitance on the VIN input voltage pin. Additional bulk capacitance may also be required for the VIN input. The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 25-V voltage rating is selected to support the maximum input voltage. The input capacitance value impacts the input ripple voltage of the regulator. The minimum input capacitance can be estimated using Equation 11.

Equation 11.

Here ΔV_IN is the input voltage ripple in steady state. Using the design example values, I_OUT = 10 A, V_OUT = 1.2 V, V_IN(MIN) = 9 V, F_SW = 2 MHz and ΔV_IN = 25 mV, Equation 11 yields an input capacitance of 39 µF. For this example, two 10µF, 25-V and a single 22-µF, 25-V ceramic capacitors in parallel have been selected for the VIN voltage rail. Because ESR is typically fairly low in ceramic capacitors, it is not included in this calculation.

The capacitor must also have a ripple current rating greater than the maximum input current ripple to the device during full load. The input ripple current can be calculated using Equation 12.

Equation 12.

For this example design, the RMS input ripple current is 2.21 A (RMS). The ripple current can be assumed to be shared equally between the input capacitors.

8.2.2.7 Series Capacitor Selection

A major function of the series capacitor is energy transfer. This is a different role from input and output capacitors where decoupling is the primary function. In many ways, the series capacitor is similar to the capacitor used for energy transfer in SEPIC converters and can be designed accordingly. A design objective may be to ensure the series capacitor voltage ripple does not exceed 5% to 10% of the nominal voltage under the worst case conditions. The series capacitor voltage ripple is given by Equation 13.

Equation 13.

Here C_t is the series capacitance. Equation 13 can be rearranged to provide the design equation for series capacitor selection which is

Equation 14.

where k_Ct represents the voltage ripple percentage. For example, if the voltage ripple target is 5%, the value for k_Ct is 0.05. The largest voltage ripple occurs at full load current (highest I_OUT), highest duty ratio (lowest input voltage/highest output voltage), and lowest frequency. For this design example, the value for k_Ct was selected to be 0.08. The resulting series capacitance calculated is 1.85 µF. A 10 V, X7R ceramic capacitor with 2.2 µF of capacitance is selected.

Another aspect to consider is capacitor RMS current rating. This impacts the temperature rise of the capacitor. Check the capacitor datasheet for temperature rise information. If the temperature rise is too large for a single capacitor, multiple capacitors may be placed in parallel to share the RMS current. The series capacitor has the same current profile as the high side MOSFETs. The RMS current squared can be expressed as

Equation 15.

where I_L(RMS) is the RMS inductor current of either inductor. The series capacitor RMS current can be expressed as

Equation 16.

where ΔIL is the inductor current ripple. The largest RMS current occurs at the highest load current and highest duty ratio.

Multilayer ceramic capacitors (MLCC) are well suited for operating as the series capacitor. The equivalent series resistance (ESR) is relatively low (for example, 5 mΩ to 10 mΩ) which helps to reduce power loss and self heating. The equivalent series inductance (ESL) is fairly low which results in a high self resonant frequency (SRF). There are a few key items that should be considered when designing. First, the effective capacitance decreases with DC bias. This means that the capacitor should be selected based on its capacitance with the nominal voltage of V_IN/2 applied. Temperature variation also reduces effective capacitance. For this reason, X7R capacitors with up to 125°C operating temperature range are recommended. If capacitors are not properly selected, cracking or other failure modes may result.

8.2.2.8 Soft-Start Time Selection

The soft-start time is the amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the desired output voltage level. The large currents necessary to charge the capacitor may make the TPS54A20 reach the current limit and trigger a fault. Excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft-start time can be selected using the resistor values listed in Table 1. For the example circuit, the soft-start time is not critical since the output capacitor value is 94 µF which does not require a large amount of current to charge to 1.2 V. For this example design, the average output current is approximately 220 mA during soft start. The example circuit has the soft start time set to 512 µs which requires no resistor (open connection) on the SS/FSEL pin. The average converter output current required to charge the output capacitors to the target output voltage during soft start can be estimated using Equation 17.

Equation 17.

8.2.2.9 Bootstrap Capacitor Selection

A 0.047 μF ceramic capacitor should be connected between the BOOTA to SCAP pins and between the BOOTB and SWB pins for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or higher voltage rating.

8.2.2.10 Gate Drive Capacitor Selection

A 1 μF ceramic capacitor should be connected between VGA and PGND and between the VG+ and VG- pins for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The VGA capacitor should have 16 V or higher voltage rating and the VG+ capacitor should have 10 V or higher voltage rating.

8.2.2.11 Under Voltage Lockout Set Point

The Under Voltage Lock Out (UVLO) set point can be adjusted using an external voltage divider network. The top resistor is connected between VIN and the EN pin and bottom resistor is connected between EN and GND as shown in Figure 42. For the example design, the supply should turn on and start switching once the input voltage increases above 9.4 V (UVLO start or enable). After the regulator starts switching, it should continue to do so until the input voltage falls below 9.2 V (UVLO stop or disable). The resistor values for obtaining the desired UVLO thresholds can be calculated using Equation 18 and Equation 19. R_EN,TOP, the top UVLO divider resistor, is calculated using Equation 18. R_EN,BOT, the bottom UVLO divider resistor, is calculated in Equation 19.

Equation 18.

Equation 19.

For the start and stop voltages specified the resistor value selected for R_EN,TOP (R2) is 80.6 kΩ and for R_EN,BOT (R3) is 12.4 kΩ.

8.2.2.12 Current Limit Selection

The current limit can be selected using the ILIM pin. Refer to Table 2 for resistor selection information. It is recommended to choose a current limit that is 1.5 times or more than the full load current expected in the application. This allows for margin in the inductor currents when responding to load transients and limits nuisance trips.