SLVSEQ0A May   2019  – March 2020 TPS54A24

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Simplified Schematic
  3. 3 Description
    1.     Efficiency (VIN = 12 V, fSW = 500 kHz)
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Continuous Conduction Mode Operation (CCM)
      3. 7.3.3  VIN Pins and VIN UVLO
      4. 7.3.4  Voltage Reference and Adjusting the Output Voltage
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Enable and Adjustable UVLO
      7. 7.3.7  Soft Start and Tracking
      8. 7.3.8  Safe Start-Up Into Prebiased Outputs
      9. 7.3.9  Power Good
      10. 7.3.10 Sequencing (SS/TRK)
      11. 7.3.11 Adjustable Switching Frequency (RT Mode)
      12. 7.3.12 Synchronization (CLK Mode)
      13. 7.3.13 Bootstrap Voltage and 100% Duty Cycle Operation (BOOT)
      14. 7.3.14 Output Overvoltage Protection (OVP)
      15. 7.3.15 Overcurrent Protection
        1. 7.3.15.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.15.2 Low-Side MOSFET Overcurrent Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Output Voltage Resistors Selection
        7. 8.2.2.7  Soft-Start Capacitor Selection
        8. 8.2.2.8  Undervoltage Lockout Setpoint
        9. 8.2.2.9  Bootstrap Capacitor Selection
        10. 8.2.2.10 PGOOD Pullup Resistor
        11. 8.2.2.11 Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = -40°C to 150°C, V(VIN) = 4.5 V to 17 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE
UVLO_rise VIN undervoltage lockout V(VIN) rising 4.1 4.3 V
UVLO_fall V(VIN) falling 3.7 3.9 V
UVLO_hys Hysteresis VIN voltage 0.2 V
Ivin Operating non-switching supply current V(EN) = 5 V, V(FB) = 1.5 V 580 800 µA
Ivin_sdn Shutdown supply current V(EN) = 0 V 3 11 µA
ENABLE
Ven_rise EN threshold V(EN) rising 1.20 1.26 V
Ven_fall V(EN) falling 1.1 1.15 V
Ven_hys EN pin threshold voltage hysteresis 50 mV
Ip EN pin sourcing current V(EN) = 1.1V 1.2 µA
Iph EN pin sourcing current V(EN) = 1.3V 4.8 µA
Ih EN pin hysteresis current 3.6 µA
FB
VFB Regulated FB voltage TJ = 25°C 596 600 604 mV
595 600 605 mV
ERROR AMPLIFIER
gmea Error amplifier transconductance (gm) –2 µA < I(COMP) < 2 µA, V(COMP) = 1 V 1100 µA/V
Error amplifier DC gain 80 dB
Icomp_src Error amplifier source current V(FB) = 0 V 100 µA
Icomp_snk Error amplifier sink current V(FB) = 2 V -100 µA
gmps Power stage transconductance 17 A/V
SS/TRK
Iss Soft start current 5 µA
V(SS/TRK) to V(FB) matching V(SS/TRK) = 0.4 V 30 mV
MOSFET
Rds(on)_h High-side switch resistance (VIN pins to SW pins) TA = 25°C, V(VIN) = 12 V 21 mΩ
TA = 25°C, V(VIN) = 4.5 V, V(BOOT-SW) = 4.5 V 23 mΩ
Rds(on)_l Low-side switch resistance (SW pins to PGND pins) TA = 25°C, V(VIN) = 12 V 8 mΩ
TA = 25°C, V(VIN) = 4.5 V 9 mΩ
BOOT UVLO Falling 2.2 2.6 V
CURRENT LIMIT
Ioc_HS_pk High-side peak current limit V(VIN) = 12 V, TJ = 25℃ 13.4 14.6 15.8 A
Ioc_LS_snk Low-side sinking current limit V(VIN) = 12 V -3.4 A
Ioc_LS_src Low-side sourcing current limit V(VIN) = 12 V 10 12.9 14.6 A
RT/CLK
VIH Logic high input voltage 2 V
VIL Logic low input voltage 0.8 V
PGOOD
Power good threshold V(FB) rising (fault) 104% 108%
V(FB) falling (good) 106%
V(FB) rising (good) 91%
V(FB) falling (fault) 89% 95%
Ipg_lkg Leakage current into PGOOD pin when pulled high V(PGOOD) = 5 V 5 nA
Vpg_low PGOOD voltage when pulled low I(PGOOD) = 2 mA 0.18 0.22 V
Minimum VIN for valid output V(PGOOD) < 0.5 V, I(PGOOD) = 2.5 mA 0.9 1 V
THERMAL PROTECTION
TTRIP Thermal protection trip point Temperature rising 170 °C
THYST Thermal protection hysteresis 15 °C