SLVSEQ0A May 2019 – March 2020 TPS54A24
PRODUCTION DATA.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 1 | – | Ground of internal analog circuitry. AGND must be connected to PGND for proper operation. Connect to PGND in a region outside of the critical switching loop. |
VIN | 2, 3, 16, 17 | I | Input voltage supply pin. Power for the internal circuit and the connection to drain of high-side MOSFET. Connect both pins to the input power source with a low impedance connection. Connect both pins and their neighboring PGND pins. |
PGND | 4, 5, 6, 7, 12, 13, 14, 15 | – | Ground return for low-side power MOSFET and its drivers. |
SW | 8, 9, 10, 11 | O | Switching node. Connected to the source of the high-side MOSFET and drain of the low-side MOSFET. |
BOOT | 18 | I | Floating supply voltage for high-side MOSFET gate drive circuit. Connect a 0.1-µF ceramic capacitor between BOOT and SW pins. |
PGOOD | 19 | O | Open-drain power good indicator. It is asserted low if output voltage is outside if the PGOOD thresholds, VIN is low, EN is low, device is in thermal shutdown or device is in soft start. |
EN | 20 | I | Enable pin. Float or pull high to enable the device. Connect a resistor divider to this pin to implement adjustable under voltage lockout and hysteresis. |
SS/TRK | 21 | I | Soft-start and tracking pin. Connecting an external capacitor sets the soft-start time. This pin can also be used for tracking and sequencing. |
COMP | 22 | I | Error amplifier output and input to the PWM modulator. Connect loop compensation to this pin. |
FB | 23 | I | Converter feedback input. Connect to the output voltage with a resistor divider. |
RT/CLK | 24 | I | Switching frequency setting pin. In RT mode, an external timing resistor adjusts the switching frequency. In CLK mode, the device synchronizes to an external clock input to this pin. |
Thermal PAD | – | – | Exposed thermal pad. Connect to PGND pins and to internal ground planes using multiple vias for good thermal performance. |