SLVSES4D September 2019 – June 2024 TPS54J060
PRODUCTION DATA
The TPS54J060 monitors the FB voltage to detect overvoltage and undervoltage. When the FB voltage becomes lower than 80% of the VINTREF voltage, the UVP comparator detects and an internal UVP delay counter begins counting. After the 64-µs UVP delay time, the latches OFF both high-side and low-side FETs drivers. The UVP function enables after the soft-start period is complete.
When the FB voltage becomes higher than 116% of the VINTREF voltage, the OVP comparator detects and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching a negative current limit INOCL. Upon reaching the negative current limit, the low-side FET is turned off, and the high-side FET is turned on again, for the on-time determined by VIN, VOUT, and fSW. The device operates in this cycle until the output voltage is pulled down under the UVP threshold voltage for 64 µs. After the 64-µs UVP delay time, both high-side and low-side FETs latch off. The fault is cleared with a reset of the input voltage or by re-toggling the EN pin.
During the UVP delay time, if the output voltage becomes higher than the UV threshold, so it is not qualified for UV event and the timer is reset to zero. When the output voltage triggers the UV threshold again, the UVP delay timer restarts.