SLVSFQ0B October   2020  – June 2024 TPS54J061

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Enable and Internal LDO
      2. 6.3.2  Split Rail and External LDO
      3. 6.3.3  Output Voltage Setting
      4. 6.3.4  Soft Start and Output-Voltage Tracking
      5. 6.3.5  Frequency and Operation Mode Selection
      6. 6.3.6  D-CAP3™ Control Mode
      7. 6.3.7  Current Sense and Positive Overcurrent Protection
      8. 6.3.8  Low-side FET Negative Current Limit
      9. 6.3.9  Power Good
      10. 6.3.10 Overvoltage and Undervoltage Protection
      11. 6.3.11 Out-Of-Bounds Operation (OOB)
      12. 6.3.12 Output Voltage Discharge
      13. 6.3.13 UVLO Protection
      14. 6.3.14 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Auto-Skip Eco-Mode Light Load Operation
      2. 6.4.2 Forced Continuous-Conduction Mode
      3. 6.4.3 Pre-Bias Start-up
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Choose the Switching Frequency and Operation Mode (MODE Pin)
        2. 7.2.2.2  Choose the Output Inductor (L)
        3. 7.2.2.3  Set the Current Limit (TRIP)
        4. 7.2.2.4  Choose the Output Capacitors (COUT)
        5. 7.2.2.5  Choose the Input Capacitors (CIN)
        6. 7.2.2.6  Feedback Network (FB Pin)
        7. 7.2.2.7  Soft Start Capacitor (SS/REFIN Pin)
        8. 7.2.2.8  EN Pin Resistor Divider
        9. 7.2.2.9  VCC Bypass Capacitor
        10. 7.2.2.10 BOOT Capacitor
        11. 7.2.2.11 Series BOOT Resistor and RC Snubber
        12. 7.2.2.12 PGOOD Pullup Resistor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Support Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Trademarks
    5. 8.5 Glossary
    6. 8.6 Electrostatic Discharge Caution
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Ordering Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

TJ = –40°C to +125°C, VCC = 3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ(VIN) VIN operating non-switching supply current VEN = 2 V, VFB = VINTREF + 50mV, VIN = 12 V, no external bias on VCC pin 750 900 µA
IQ(VCC) External VCC bias current(1) 3.3 V external bias on VCC pin, fSW(FCCM) = 600kHz 3 mA
3.3 V external bias on VCC pin, fSW(FCCM) = 1100kHz 5.5 mA
3.3 V external bias on VCC pin, fSW(FCCM) = 2200kHz 10 mA
ISD_VIN VIN shutdown supply current VEN = 0 V, VIN =12 V, no external bias on VCC pin 10 µA
VINUVLO(R) VIN UVLO rising threshold voltage VIN rising, VCC = external 3.3V bias  2.1 2.4 2.7 V
VINUVLO(F) VIN UVLO falling threshold voltage VIN falling, VCC = external 3.3V bias 1.55 1.85 2.15 V
ENABLE
VENH EN enable threshold voltage (rising) 1.17 1.22 1.27 V
VENL EN disable threshold voltage (falling) 0.97 1.02 1.07 V
VENHYST EN hysteresis voltage 0.2 V
VENLEAK EN input leakage current VEN = 3.3 V –5 0 5 µA
EN internal pull-down resistance EN pin to AGND. 6500 kΩ
INTERNAL LDO
VCC Internal LDO output voltage VIN = 12 V, IVCC(LOAD) = 5 mA 2.90 3.00 3.10 V
VCCUVLO VCC undervoltage-lockout (UVLO) threshold voltage VCC rising 2.80 2.85 2.90 V
VCC falling 2.65 2.70 2.75 V
VCCUVLO VCC undervoltage-lockout (UVLO) threshold voltage VCC hysteresis 0.15 V
VCCDO LDO low-droop dropout voltage VIN = 3.3 V, IVCC(LOAD) = 20 mA, TJ = 25°C 310 mV
LDO overcurrent limit All VINs, all temps 30 60 mA
REFERENCE
VINTREF Internal REF voltage TJ = 25°C 600 mV
Internal REF voltage tolerance TJ = 0°C to 70°C 597 603 mV
Internal REF voltage tolerance TJ = –40°C to 125°C 594 606 mV
IFB FB input current VFB = VINTREF 100 nA
SWITCHING FREQUENCY
fSW(FCCM) VO switching frequency, FCCM operation(1) VIN = 12 V, VOUT=1.2V, RMODE = 0 Ω to AGND, No Load 935 1100 1265 kHz
fSW(FCCM) VO switching frequency, FCCM operation(1) VIN = 12 V, VOUT=2.5V, RMODE = 30.1 kΩ to AGND, No Load 1870 2200 2530 kHz
fSW(FCCM) VO switching frequency, FCCM operation VIN = 12 V, VOUT=1.2V, RMODE = 60.4 kΩ to AGND, No Load 536 630 724 kHz
tON(min) Minimum on-time VIN=12V VOUT=1V, first pulse 70 95 ns
tOFF(min) Minimum off-time TJ = 25°C, HS FET Gate falling to rising 220 ns
STARTUP
EN to first switching delay, internal LDO The delay from EN goes high to the first SW rising edge with internal 3.0V LDO. VCC bypass cap = 1uF for typical value, VCC bypass cap = 2.2uF for max value. CSS/REFIN = 1nF 0.85 2 ms
EN to first switching delay, external VCC bias The delay from EN goes high to the first SW rising edge with external 3.3V VCC bias. CSS/REFIN = 1nF 500 700 µs
tSS Internal soft-start time VO rising from 0 V to 95% of final setpoint, CSS/REFIN = 1nF 1 1.5 ms
SS/REFIN sourcing current VSS/REFIN = 0 V 9 µA
SS/REFIN sinking current VSS/REFIN = 1 V 3 µA
SSREFIN Detection Threshold VIN=4V-16V, VCC=3.0V – 5.3V, -40C- 125C, TPS54J061 800 mV
SS/REFIN to FB matching VSS/REFIN = 0.5 V -5 0 5 mV
POWER STAGE
RDS(on)HS High-side MOSFET on-resistance TJ = 25°C, BOOT-SW = 3 V, IO = 3 A 22 mΩ
RDS(on)LS Low-side MOSFET on-resistance TJ = 25°C, VCC = 3 V, IO = 3 A 8.5 mΩ
BOOT CIRCUIT
IVBST-SW VBST-SW leakage current TJ = 25°C, VVBST-SW = 3.3 V 28 µA
BOOT UVLO(1) TJ = 25°C, Voltage rising 2.35 V
BOOT UVLO Hysteresis(1) TJ = 25°C 0.32 V
CURRENT DETECTION
Current limit clamp Valley current on LS FET, 0-Ω ≤ RTRIP ≤ 3.16-kΩ 8.1 9.5 A
RTRIP TRIP pin resistance range 3.74 30.1 kΩ
IOCL Current limit threshold Valley current on LS FET, RTRIP = 4.99 kΩ 5.1 6.0 6.9 A
KOCL KOCL constant for RTRIP equation 30000
KOCL tolerance 3.74-kΩ ≤ RTRIP ≤ 4.99-kΩ -10 10 %
KOCL tolerance 10-kΩ = RTRIP -16.5 16.5 %
INOCL Negative current limit threshold All VINs -4.3 –3.5 -2.8 A
IZC Zero-cross detection current threshold, open loop VIN = 12 V, VCC = 3 V 0 200 730 mA
UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP Overvoltage-protection (OVP) threshold voltage 113 116 119 %
VUVP Undervoltage-protection (UVP) threshold voltage 77 80 83 %
tdelay(OVP) OVP response delay With 100-mV overdrive 300 ns
tdelay(UVP) UVP filter delay 64 µs
tdelay(hiccup) Hiccup delay time VIN=12V, VCC=3V 14 ms
POWER GOOD
VPGTH PGOOD threshold FB rising, PGOOD transition low to high 89 92.5 95 %
FB rising, PGOOD transition high to low 113 116 119
FB falling, PGOOD transition high to low 77 80 83
VOOB PGOOD & Out-of-bounds threshold FB rising 102.5 105 107.5 %
IPG PGOOD sink current VPGOOD = 0.4 V, VIN = 12 V, VCC = 3 V 5.5 mA
IPG PGOOD low-level output voltage IPGOOD = 5.5 mA, VIN = 12 V, VCC = 3 V 400 mV
tdelay(PG) PGOOD delay time Delay for PGOOD from low to high 1 1.25 ms
Delay for PGOOD from high to low 2 5 µs
Ilkg(PG) PGOOD leakage current when pulled high TJ = 25°C, VPGOOD = 3.3 V, VFB = VINTREF 5 µA
PGOOD clamp low-level output voltage VIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD pulled up to 3.3 V through a 100-kΩ resistor 750 1100 mV
VIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD pulled up to 3.3 V through a 10-kΩ resistor 950 1250 mV
Min VCC for valid PGOOD output 1.5 V
OUTPUT DISCHARGE
RDischg Output discharge resistance VIN = 12 V, VCC = 3 V, power conversion disabled 80 Ω
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold(1) Temperature rising 155 170 °C
Thermal shutdown hysteresis(1) 38 °C
(1) Specified by design. Not production tested.