SNVSB02C March   2020  – July 2021 TPS54JA20

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO And Using External Bias On VCC Pin
      2. 7.3.2  Enable
      3. 7.3.3  Output Voltage Setting
        1. 7.3.3.1 Remote Sense
      4. 7.3.4  Internal Fixed Soft Start and External Adjustable Soft Start
      5. 7.3.5  External REFIN For Output Voltage Tracking
      6. 7.3.6  Frequency and Operation Mode Selection
      7. 7.3.7  D-CAP3 Control
      8. 7.3.8  Low-side FET Zero-Crossing
      9. 7.3.9  Current Sense and Positive Overcurrent Protection
      10. 7.3.10 Low-side FET Negative Current Limit
      11. 7.3.11 Power Good
      12. 7.3.12 Overvoltage and Undervoltage Protection
      13. 7.3.13 Out-Of-Bounds (OOB) Operation
      14. 7.3.14 Output Voltage Discharge
      15. 7.3.15 UVLO Protection
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Powering The Device From A 12-V Bus
      4. 7.4.4 Powering The Device From A 3.3-V Bus
      5. 7.4.5 Powering The Device From A Split-rail Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Output Voltage Setting Point
        2. 8.2.2.2  Choose the Switching Frequency and the Operation Mode
        3. 8.2.2.3  Choose the Inductor
        4. 8.2.2.4  Set the Current Limit (TRIP)
        5. 8.2.2.5  Choose the Output Capacitor
        6. 8.2.2.6  Choose the Input Capacitors (CIN)
        7. 8.2.2.7  Soft Start Capacitor (SS/REFIN Pin)
        8. 8.2.2.8  EN Pin Resistor Divider
        9. 8.2.2.9  VCC Bypass Capacitor
        10. 8.2.2.10 BOOT Capacitor
        11. 8.2.2.11 PGOOD Pullup Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Performance On TI EVM
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.2 Choose the Switching Frequency and the Operation Mode

The switching frequency and operation mode are configured by the resistor on MODE pin. Select one of three switching frequencies: 600 kHz, 800 kHz, or 1 MHz. Refer to Table 7-1 for the relationship between the switching frequency, operation mode and RMODE.

Switching frequency selection is a tradeoff between higher efficiency and smaller system solution size. Lower switching frequency yields higher overall efficiency but relatively bigger external components. Higher switching frequencies cause additional switching losses which impact efficiency and thermal performance. For this design, a 243-kΩ resistor is chosen for MODE pin to set the switching frequency to 0.8 MHz and set operation mode as skip mode.

When selecting the switching frequency of a buck converter, the minimum on-time and minimum off-time must be considered. Equation 8 calculates the maximum fSW before being limited by the minimum on-time. When hitting the minimum on-time limits of a converter with D-CAP3 control, the effective switching frequency will change to keep the output voltage regulated. This calculation ignores resistive drops in the converter to give a worst case estimation.

Equation 8. GUID-C149F4B1-E9BB-4B34-9CE2-A9383CCC0DB0-low.gif

Equation 8 calculates the maximum fSW before being limited by the minimum off-time. When hitting the minimum off-time limits of a converter with D-CAP3 control, the operating duty cycle will max out and the output voltage will begin to drop with the input voltage. This equation requires the DC resistance of the inductor, RDCR, selected in the following step so this preliminary calculation assumes a resistance of 2.2 mΩ. If operating near the maximum fSW limited by the minimum off-time, the variation in resistance across temperature must be considered when using Equation 9. The selected fSW of 800 kHz is below the two calculated maximum values.

Equation 9. GUID-C095988A-F2BA-4009-974B-7331990AB4EA-low.gif