The TPS55010 is a transformer driver designed to provide isolated power for isolated interfaces, such as RS-485 and RS-232, from 3.3 V or 5 V input supply.
The device uses fixed frequency current mode control and half bridge power stage with primary side feedback to regulate the output voltage for power levels up to 2W. The switching frequency is adjustable from 100 kHz to 2000 kHz so solution size, efficiency and noise can be optimized. The switching frequency is set with a resistor or is synchronized to external clock using the RT/CLK pin. To minimize inrush currents, a small capacitor can be connected to the SS pin. The EN pin can be used as an enable pin or to increase the default input UVLO voltage from 2.6V.
With the same transformer the TPS55010 can provide a solution for different input and output voltage combinations by adjusting the primary side voltage. Off the shelf transformers are available to provide single positive, or dual positive and negative output voltages.
The TPS55010 is available in a 3mm x 3mm 16 pin QFN package with thermal pad.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS55010 | WQFN (16) | 3.00 mm × 3.00 mm |
Changes from A Revision (June 2011) to B Revision
Changes from * Revision (April 2010) to A Revision
Name | Number | Description |
---|---|---|
VIN | 1, 2, 16 | Supplies the control circuitry and switches of the power converter. |
GND | 3, 4, 5 | Power Ground. This pin should be electrically connected directly to the thermal pad under the IC. |
VSENSE | 6 | Inverting node of the transconductance error amplifier. |
COMP | 7 | Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. |
RT/CLK | 8 | Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor set function. |
SS | 9 | Slow-start. An external capacitor connected to this pin sets the output rise time. |
PH | 10, 11, 12 | The source of the internal high side power MOSFET, and drain of the internal low side MOSFET. |
BOOT | 13 | A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. |
FAULT | 14 | An open drain output. Active low if the output voltage is low due to thermal shutdown, dropout, overvoltage or EN shut down. |
EN | 15 | Enable pin, internal pull-up current source. Pull below 1.2V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. |
THERMAL PAD | 17 | GND pin should be connected to the exposed thermal pad for proper operation. This thermal pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance. |