SLVSAV0B April 2011 – October 2014 TPS55010
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | VIN | –0.3 | 7 | V |
EN | –0.3 | 3.6 | V | |
BOOT | PH + 7 | V | ||
VSENSE | –0.3 | 3 | V | |
COMP | –0.3 | 3 | V | |
FAULT | –0.3 | 7 | V | |
SS | –0.3 | 3 | V | |
RT/CLK | –0.3 | 6 | V | |
BOOT-PH | –0.3 | 7 | V | |
PH | –0.6 | 7 | V | |
PH, 10ns Transient | –2 | 10 | V | |
Current | EN | 100 | µA | |
RT/CLK | 100 | µA | ||
COMP | 100 | uA | ||
FAULT | 10 | mA | ||
SS | 100 | µA | ||
Operating Junction Temperature | –40 | 150 | °C |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Tstg | Storage Temperature | –65 | 150 | °C | |
V(ESD) | Electrostatic Discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) | –2 | 2 | kV |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) | –500 | 500 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VI | Input voltage | 2.98 | 6 | V | |
PO | Output power | 2 | W |
THERMAL METRIC(1) | TPS55010 | UNIT | |
---|---|---|---|
RTE (16 PINS) | |||
θJA | Junction-to-ambient thermal resistance | 60 | °C/W |
θJCtop | Junction-to-case (top) thermal resistance | 55.5 | |
θJB | Junction-to-board thermal resistance | 24.9 | |
ψJT | Junction-to-top characterization parameter | 1.0 | |
ψJB | Junction-to-board characterization parameter | 24.9 | |
θJCbot | Junction-to-case (bottom) thermal resistance | 9.9 |
DESCRIPTION | CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
SUPPLY VOLTAGE | |||||
Operating input voltage | VIN | 2.95 | 6 | V | |
Shutdown current | EN = 0V, 25°C | 2 | 5 | µA | |
Operating current | VSENSE = 0.9V, 25°C | 360 | 575 | µA | |
Internal undervoltage lockout | 2.6 | 2.9 | V | ||
ENABLE | |||||
Enable threshold | rising | 1.25 | 1.37 | V | |
falling | 1.15 | 1.18 | |||
Input current | Threshold - 50mV | –1.2 | µA | ||
Threshold + 50mV | –4.6 | µA | |||
Hysteresis | 3.4 | ||||
VOLTAGE REFERENCE | |||||
Reference | 3V < VIN < 6V | 0.804 | 0.829 | 0.854 | V |
MOSFET | |||||
High side switch resistance | BOOT- PH = 5 V | 45 | 81 | mΩ | |
Low side switch resistance | VIN = 5 V | 45 | 81 | mΩ | |
ERROR AMPLIFIER | |||||
Input current | 50 | nA | |||
Error amp transconductance | -2 µA < I(COMP) < 2 µA | 245 | uS | ||
Error amp dc gain | VSENSE = 0.8 V | 500 | V/V | ||
Minimum unity gain Bandwidth | 3 | MHz | |||
Error amp source/sink | V(COMP) = 1V, 100 mV overdrive | ±16 | µA | ||
COMP to Iph gm | I(PH) = 0.5 A | 7.5 | A/V | ||
CURRENT LIMIT | |||||
High side sourcing current limit | VIN = 3 V | 2 | 2.75 | A | |
Low Side Sinking Current Limit | VIN = 3 V | –3 | –4.5 | A | |
THERMAL SHUTDOWN | |||||
Thermal Shutdown | 171 | °C | |||
OT Hysteresis | 12 | °C | |||
RT/CLK | |||||
RT/CLK voltage | R(RT/CLK) = 195 kΩ | 0.5 | V | ||
RT/CLK high threshold | 1.6 | 2.2 | V | ||
RT/CLK low threshold | 0.4 | 0.6 | V | ||
BOOT | |||||
Boot UVLO | 2.5 | V | |||
SS Slow Start | |||||
Charge current | V(SS) = 0.4 V | 0.5 | 2.2 | 4 | µA |
SS to VSENSE matching | V(SS) = 0.4 V | 35 | mV | ||
SS to reference Crossover | 98% reference | 1.1 | V | ||
SS discharge current (overload) | VSENSE = 0 V | 325 | µA | ||
SS discharge voltage | VSENSE = 0V | 46 | mV | ||
SS discharge current (UVLO, EN, thermal fault) | V(SS) = 0.5 V | 1.2 | mA | ||
VIN UVLO to SS start time | 100 | µs | |||
FAULT Pin | |||||
VSENSE threshold | VSENSE falling | 91 | % VREF | ||
VSENSE rising | 108 | % VREF | |||
Output high leakage | VSENSE = VREF, V(FAULT) = 5.5 V | 2 | nA | ||
Output low | I(FAULT) = 3 mA | 0.3 | V | ||
Minimum VIN for valid output | V(FAULT) < 0.5 V at 100 µA | 1.6 | V |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
RT/CLK | |||||
Minimum CLK pulse width | 75 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PH | ||||||
ton | Minimum on time | Measured at 10% to 10% of VIN | 130 | ns | ||
toff | Minimum off time | V(BOOT-PH) ≥ 3 V | 0% | |||
RT/CLK | ||||||
Switching frequency using CLK mode | 300 | 2000 | kHz | |||
Switching frequency using RT mode | 100 | 2000 | kHz | |||
Switching Frequency | R(RT/CLK) = 195 kΩ | 400 | 500 | 600 | kHz | |
PLL lock in time | 50 | µs | ||||
RT/CLK falling edge to PH rising edge delay | 90 | ns | ||||
SS Slow Start | ||||||
VIN UVLO to SS start time | 100 | µs |