SLVSFQ7A December   2020  – December 2021 TPS55288-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VCC Power Supply
      2. 7.3.2  Operation Mode Setting
      3. 7.3.3  Input Undervoltage Lockout
      4. 7.3.4  Enable and Programmable UVLO
      5. 7.3.5  Soft Start
      6. 7.3.6  Shutdown and Load Discharge
      7. 7.3.7  Switching Frequency
      8. 7.3.8  Switching Frequency Dithering
      9. 7.3.9  Inductor Current Limit
      10. 7.3.10 Internal Charge Path
      11. 7.3.11 Output Voltage Setting
      12. 7.3.12 Output Current Monitoring and Cable Voltage Droop Compensation
      13. 7.3.13 Integrated Gate Drivers
      14. 7.3.14 Output Current Limit
      15. 7.3.15 Overvoltage Protection
      16. 7.3.16 Output Short Circuit Protection
      17. 7.3.17 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Mode
      2. 7.4.2 Power Save Mode
    5. 7.5 Programming
      1. 7.5.1 Data Validity
      2. 7.5.2 START and STOP Conditions
      3. 7.5.3 Byte Format
      4. 7.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 7.5.5 Slave Address and Data Direction Bit
      6. 7.5.6 Single Read and Write
      7. 7.5.7 Multi-Read and Multi-Write
    6. 7.6 Register Maps
      1. 7.6.1 REF Register (Address = 0h, 1h) [reset = 11010010h, 00000000h]
      2. 7.6.2 IOUT_LIMIT Register (Address = 2h) [reset = 11100100h]
      3. 7.6.3 VOUT_SR Register (Address = 3h) [reset = 00000001h]
      4. 7.6.4 VOUT_FS Register (Address = 4h) [reset = 00000011h]
      5. 7.6.5 CDC Register (Address = 5h) [reset = 11100000h]
      6. 7.6.6 MODE Register (Address = 6h) [reset = 00100000h]
      7. 7.6.7 STATUS Register (Address = 7h) [reset = 00000011h]
      8. 7.6.8 Register Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Switching Frequency
        3. 8.2.2.3 Output Voltage Setting
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Input Capacitor
        6. 8.2.2.6 Output Capacitor
        7. 8.2.2.7 Output Current Limit
        8. 8.2.2.8 Loop Stability
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = -40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLY
VINInput voltage range2.736V
VVIN_UVLOUnder voltage lockout thresholdVIN rising2.82.93.0V
VIN falling2.62.652.7V
IQQuiescent current into the VIN pinIC enabled, no load, no switching. VIN = 3 V to 24 V, VOUT = 0.8 V, VFB = VREF + 0.1 V, RFSW = 100 kΩ, TJ up to 125°C760860µA
Quiescent current into the VOUT pinIC enabled, no load, no switching, VIN = 2.9 V, VOUT = 3 V to 20 V, VFB = VREF + 0.1 V, RFSW = 100 kΩ, TJ up to 125°C760860µA
ISDShutdown current into the VIN pinIC disabled, VIN = 2.9 V to 14 V, TJ up to 125°C6.810µA
VCCInternal regulator outputIVCC = 50 mA, VIN = 8 V, VOUT = 20 V5.05.25.4V
VCC_DOVCC dropoutVIN = 5.0 V, VOUT = 20 V, IVCC = 60 mA200320mV
VIN = 14 V, VOUT = 5.0 V, IVCC = 60 mA110170mV
EN/UVLO
VEN_HEN Logic high thresholdVCC = 2.7 V to 5.5 V1.15V
VEN_LEN Logic low thresholdVCC = 2.7 V to 5.5 V0.4V
VEN_HYSEnable threshold hysteresisVCC = 2.7 V to 5.5 V0.050.12V
VUVLOUVLO rising threshold at the EN/UVLO pinVCC = 3.0 V to 5.5 V1.201.231.26V
VUVLO_HYSUVLO threshold hysteresisVCC = 3.0 V to 5.5 V81420mV
IUVLOSourcing current at the EN/UVLO pinVEN/UVLO = 1.3 V4.555.5µA
OUTPUT
VOUTOutput voltage range0.822V
VOVPOutput overvoltage protection threshold22.523.524.5V
VOVP_HYSOver voltage protection hysteresis1V
IFB_LKGLeakage current at the FB pinTJ up to 125°C100nA
IVOUT_LKGLeakage current into the VOUT pinIC disabled, VOUT = 20 V, VSW2 = 0 V, TJ up to 125°C120µA
IDISCHGOutput discharge currentVOUT = 20 V, VCC = 5.2 V40100170mA
INTERNAL REFERENCE DAC
Resolution of reference voltage DAC10bits
INLIntegral non-linearity–44LSB
DNLDifferential non-linearity–12LSB
VOUT_FULLOutput voltage when VREF is set to 1.129VVOUT_FS=03h, REF=03C0h, VREF = 1.129 V19.72020.3V
VOUT_FS=02h, REF=03C0h, VREF=1.129V14.781515.22V
VOUT_FS=01h, REF=03C0h, VREF = 1.129 V9.851010.15V
VOUT_FS=00h, REF=03C0h, VREF = 1.129 V4.9355.07V
VOUT_ZEROOutput voltage when VREF is set to 45mVVOUT_FS=03h, REF=0000h, VREF = 45 mV0.740.80.86V
VOUT_FS=02h, REF=0000h, VREF = 45 mV0.560.60.64V
VOUT_FS=01h, REF=0000h, VREF = 45 mV0.370.40.43V
VOUT_FS=00h, REF=0000h, VREF = 45 mV0.180.20.22V
REFERENCE VOLTAGE
VREFReference voltage at the FB/INT pin when using external feedbackExternal feedback with REF=03C0h1.1171.1291.141V
External feedback with REF=02C6h0.8370.8460.855V
External feedback with REF=019Ah0.5020.5080.514V
External feedback with REF=00D2h0.2760.2820.288V
POWER SWITCH
RDS(on)Low-side MOSFET on resistance on boost sideVOUT = 20 V, VCC= 5.2 V7.1mΩ
High-side MOSFET on resistance on boost sideVOUT = 20 V, VCC= 5.2 V7.6mΩ
INTERNAL CLOCK
fSWSwitching frequencyRFSW = 100 kΩ180200220kHz
RFSW = 9.09 kΩ200022002400kHz
tOFF_minMin. off timeBoost mode100145ns
tON_minMin. on timeBuck mode90130ns
VFSWVoltage at the FSW pin1V
CURRENT LIMIT
ILIM_AVGAverage inductor current limitRILIM = 20 kΩ, VIN = 8 V, VOUT = 20 V, fSW = 400 kHz, FPWM1416.519A
RILIM = 20 kΩ, VIN = 8 V, VOUT = 20 V, fSW = 400 kHz, PFM1416.519A
RILIM = 60 kΩ, VIN = 5 V, VOUT = 14 V, fSW = 2.2 MHz, FPWM45.5A
RILIM = 60 kΩ, VIN = 5 V, VOUT = 14 V, fSW = 2.2 MHz, PFM45.5A
ILIM_PKPeak inductor current limit at high sideRILIM = 20 kΩ, VIN = 8 V, VOUT = 20 V, fSW = 400 kHz, FPWM25A
RILIM = 20 kΩ, VIN = 8 V, VOUT = 20 V, fSW = 400 kHz, PFM25A
VILIMVoltage at the ILIM pinVOUT = 3 V0.6V
VSNSCurrent loop regulation voltage between the ISP and ISN pinsVISN = 2 V to 21 V,IOUT_LIMIT Register = 11100100b485052mV
VISN = 2 V to 21 V,IOUT_LIMIT Register = 10111100b283032mV
CABLE VOLTAGE DROOP COMPENSATION
VCDCVoltage at the CDC pinRCDC = 20 kΩ or floating, VISP – VISN = 50 mV0.9511.05V
RCDC = 20 kΩ or floating, VISP – VISN = 2 mV4075mV
VOUT_CDCVOUT increase for cable droop compensationInternal output feedback, CDC[2:0]=111, VISP – VISN = 50 mV650700750mV
Internal output feedback, CDC[2:0]=111, VISP – VISN = 2 mV3060mV
Internal output feedback, CDC[2:0]=001, VISP – VISN = 50 mV70100130mV
Internal output feedback, CDC[2:0]=001, VISP – VISN = 10 mV2040mV
IFB_CDCFB/INT  pin sinking currentExternal output feedback, RCDC = 20kΩ, VISP – VISN = 50 mV7.237.57.87µA
External output feedback, RCDC = 20 kΩ, VISP – VISN = 0 mV0.050.32µA
External output feedback, RCDC = floating, VISP – VISN = 50 mV00.3µA
ERROR AMPLIFIER
ISINKCOMP pin sink currentVFB = VREF + 400 mV, VCOMP = 1.5 V, VCC = 5 V20µA
ISOURCECOMP pin source currentVFB = VREF - 400 mV, VCOMP = 1.5 V, VCC = 5 V60µA
VCCLPHHigh clamp voltage at the COMP pin1.8V
VCCLPLLow clamp voltage at the COMP pin0.7V
GEAError amplifier transconductance190µA/V
SOFT START
tSSSoft-start time345ms
DR1H GATE DRIVER
VDR1H_LLow-state voltage dropVDR1H – VSW1, 100-mA sinking0.1V
VDR1H_HHigh-state voltage dropVBOOT1 – VDR1H, 100-mA sourcing0.2V
DR1L GATE DRIVER
VDR1L_LLow-state voltage drop100-mA sinking0.1V
VDR1L_HHigh-state voltage dropVCC – VDR1L, 100-mA sourcing0.2V
SPREAD SPECTRUM
IDITH_CHGDithering charge currentVDITH/SYNC = 1.0 V, RFSW = 49.9 kΩ, voltage rising from 0.85 V2µA
IDITH_DISDithering discharge currentVDITH/SYNC = 1.0 V, RFSW = 49.9 kΩ, voltage falling from 1.15 V2µA
VDITH_HDither high threshold1.07V
VDITH_LDither low threshold0.93V
SYNCHRONOUS CLOCK
VSNYC_HSync clock high voltage threshold1.2V
VSYNC_LSync clock low voltage threshold0.4V
tSYNC_MINMinimum sync clock pulse width50ns
HICCUP
tHICCUPHiccup off time76ms
MODE RESISTANCE DETECTION
IMODESourcing current from the MODE pinVMODE = 2.5 V91011µA
VMODE_DT1Detection threshold voltage at the MODE pin1.1471.2201.293V
VMODE_DT20.8240.880.936V
VMODE_DT30.5710.6140.657V
VMODE_DT40.3210.3510.381V
VMODE_DT50.1680.1890.210V
VMODE_DT60.0800.0970.114V
VMODE_DT70.0140.0270.040V
LOGIC INTERFACE
VI2C_IOIO voltage range for I2C1.75.5V
VI2C_HI2C input high thresholdVCC = 2.7 V to 5.5 V1.2V
VI2C_LI2C input low thresholdVCC = 2.7 V to 5.5 V0.4V
IFB/INT_HLeakage current into FB/INT pin when outputting high impedanceVFB/INT = 5 V100nA
VFB/INT_LOutput low voltage range of the FB/INT pinSinking 4-mA current0.030.1V
PROTECTION
TSDThermal shutdown thresholdTJ rising175°C
TSD_HYSThermal shutdown hysteresisTJ falling below TSD20°C