SLVSGT5 December   2023 TPS55289-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VCC Power Supply
      2. 6.3.2  EXTVCC Power Supply
      3. 6.3.3  I2C Address Selection
      4. 6.3.4  Input Undervoltage Lockout
      5. 6.3.5  Enable and Programmable UVLO
      6. 6.3.6  Soft Start
      7. 6.3.7  Shutdown and Load Discharge
      8. 6.3.8  Switching Frequency
      9. 6.3.9  Switching Frequency Dithering
      10. 6.3.10 Inductor Current Limit
      11. 6.3.11 Internal Charge Path
      12. 6.3.12 Output Voltage Setting
      13. 6.3.13 Output Current Monitoring and Cable Voltage Droop Compensation
      14. 6.3.14 Output Current Limit
      15. 6.3.15 Overvoltage Protection
      16. 6.3.16 Output Short Circuit Protection
      17. 6.3.17 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 PWM Mode
      2. 6.4.2 Power Save Mode
    5. 6.5 Programming
      1. 6.5.1 Data Validity
      2. 6.5.2 START and STOP Conditions
      3. 6.5.3 Byte Format
      4. 6.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 6.5.5 target Address and Data Direction Bit
      6. 6.5.6 Single Read and Write
      7. 6.5.7 Multi-Read and Multi-Write
  8. 7 Register Maps
    1. 7.1 REF Register (Address = 0h, 1h) [reset = 10100100b, 00000001b]
    2. 7.2 IOUT_LIMIT Register (Address = 2h) [reset = 11100100b]
    3. 7.3 VOUT_SR Register (Address = 3h) [reset = 00000001b]
    4. 7.4 VOUT_FS Register (Address = 4h) [reset = 00000011b]
    5. 7.5 CDC Register (Address = 5h) [reset = 11100000b]
    6. 7.6 MODE Register (Address = 6h) [reset = 00100000b]
    7. 7.7 STATUS Register (Address = 7h) [reset = 00000011b]
    8. 7.8 Register Summary
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency
        2. 8.2.2.2 Output Voltage Setting
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Output Current Limit
        7. 8.2.2.7 Loop Stability
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 MODE Register (Address = 6h) [reset = 00100000b]

MODE is shown in Figure 7-7 and described in Table 7-8.

Return to Summary Table.

MODE controls the operating mode of the TPS55289-Q1.

Figure 7-7 MODE Register
76543210
OEFSWHICCUPDISCHGForce_DISCHGReservedFPWMReserved
R/W-0bR/W-0bR/W-1bR/W-0bR/W-0bR-0bR/W-0bR-0b
Table 7-8 MODE Register Field Descriptions
BitFieldTypeResetDescription
7OER/W0bOutput enable

0b = Output disabled (Default)

1b = Output enable

6FSWDBLR/W0bSwitching frequency doubling in buck-boost mode

0b = Keep the switching frequency unchanged during buck-boost mode (Default)

1b = Double the switching frequency during buck-boost mode

5HICCUPR/W1bHiccup mode

0b = Disable the hiccup during output short circuit protection.

1b = Enable the hiccup during output short circuit protection (Default)

4DISCHGR/W0bOutput discharge

0b = Disabled VOUT discharge when the device is in shutdown mode (Default)

1b = Enable VOUT discharge. VOUT is discharged to ground by an internal 100mA current sink in shutdown mode (OE bit is cleared to 0)

3Force_DISCHGR/W0bForce output dischage

Force output discharge helps reduce the VOUT falling time in auto PFM mode when set VOUT to lower voltage. TI does not recommend enabling this bit longer than 10ms at high VOUT range (>10V) due to high power loss.

0b = Disabled VOUT discharge FET(Default)

1b = Force enable VOUT discharge FET. VOUT is discharged to ground by an internal 100mA current sink

2RESERVEDR0bReserved
1FPWMR/W0bSelect operating mode at light load condition

0b = PFM operating mode at light load condition (Default)

1b = FPWM operating mode at light load condition

0RESERVEDR0bReserved