SLVSGT5 December 2023 TPS55289-Q1
PRODUCTION DATA
STATUS is shown in Figure 7-8 and described in Table 7-9.
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The STATUS register stores the operating status of the TPS55289-Q1. When any of the SCP bit, the OCP bit, or the OVP bit are set, and the corresponding mask bit in register 05h is set as well, the FB/INTĚ… pin outputs low logic level to indicate the situation. Reading register 07h clears the SCP bit, OCP bit, and OVP bit. After the SCP bit, OCP bit, or OVP bit is set, it does not reset until the register is read. If the situation still exists, the corresponding bit is set again.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCP | OCP | OVP | Reserved | Reserved | Reserved | STATUS | |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-11b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SCP | R | 0b | Short circuit protection 0b = No short circuit 1b = Short circuit happens. Does not reset until it is read. |
6 | OCP | R | 0b | Overcurrent protection 0b = No output overcurrent 1b = Output current hits the current limit sensed at the ISP and the ISN pin. Does not reset until it is read. |
5 | OVP | R | 0b | Overvoltage protection 0b = No OVP 1b = Output voltage exceeds the OVP threshold. Does not reset until it is read. |
4 | RESERVED | R | 0b | Reserved |
3 | RESERVED | R | 0b | Reserved |
2 | RESERVED | R | 0b | Reserved |
1-0 | STATUS | R | 11b | Operating status 00b = Boost 01b = Buck 10b = Buck-Boost 11b = Reserved |