SLVSGT5 December   2023 TPS55289-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VCC Power Supply
      2. 6.3.2  EXTVCC Power Supply
      3. 6.3.3  I2C Address Selection
      4. 6.3.4  Input Undervoltage Lockout
      5. 6.3.5  Enable and Programmable UVLO
      6. 6.3.6  Soft Start
      7. 6.3.7  Shutdown and Load Discharge
      8. 6.3.8  Switching Frequency
      9. 6.3.9  Switching Frequency Dithering
      10. 6.3.10 Inductor Current Limit
      11. 6.3.11 Internal Charge Path
      12. 6.3.12 Output Voltage Setting
      13. 6.3.13 Output Current Monitoring and Cable Voltage Droop Compensation
      14. 6.3.14 Output Current Limit
      15. 6.3.15 Overvoltage Protection
      16. 6.3.16 Output Short Circuit Protection
      17. 6.3.17 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 PWM Mode
      2. 6.4.2 Power Save Mode
    5. 6.5 Programming
      1. 6.5.1 Data Validity
      2. 6.5.2 START and STOP Conditions
      3. 6.5.3 Byte Format
      4. 6.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 6.5.5 target Address and Data Direction Bit
      6. 6.5.6 Single Read and Write
      7. 6.5.7 Multi-Read and Multi-Write
  8. 7 Register Maps
    1. 7.1 REF Register (Address = 0h, 1h) [reset = 10100100b, 00000001b]
    2. 7.2 IOUT_LIMIT Register (Address = 2h) [reset = 11100100b]
    3. 7.3 VOUT_SR Register (Address = 3h) [reset = 00000001b]
    4. 7.4 VOUT_FS Register (Address = 4h) [reset = 00000011b]
    5. 7.5 CDC Register (Address = 5h) [reset = 11100000b]
    6. 7.6 MODE Register (Address = 6h) [reset = 00100000b]
    7. 7.7 STATUS Register (Address = 7h) [reset = 00000011b]
    8. 7.8 Register Summary
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency
        2. 8.2.2.2 Output Voltage Setting
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Output Current Limit
        7. 8.2.2.7 Loop Stability
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-9A1F9FAF-36C6-4274-8BE1-54FAF753475C-low.svgFigure 4-1 21-pin VQFN-HR, RYQ Package (Transparent Top View)
Table 4-1 Pin Functions
PINI/ODESCRIPTION
NO.NAME
1EN/UVLOIEnable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic high level enables the device. Logic low level disables the device and turns it into shutdown mode. After the voltage at the EN/UVLO pin is above the logic high voltage of 1.15V, this pin acts as programmable UVLO input with 1.23V internal reference.
2MODEII2C target address selection. When it is connected to logic high voltage, the I2C target address is 74H. When it is connected to logic low voltage, I2C target address is 75H.
3SCLIClock of I2C interface.
4SDAI/OData of I2C interface.
5DITH/SYNCIDithering frequency setting and synchronous clock input. Use a capacitor between this pin and ground to set the dithering frequency. When this pin is short to ground or pulled above 1.2V, there is no dithering function. An external clock can be applied at this pin to synchronize the switching frequency.
6FSWIThe switching frequency is programmed by a resistor between this pin and the AGND pin.
7VINPWRInput of the buck-boost conveter.
8SW1PWRThe switching node pin of the buck side. It is connected to the drain of the internal buck low-side power MOSFET and the source of internal buck high-side power MOSFET.
9PGNDPWRPower ground of the device.
10SW2PWRThe switching node pin of the boost side. It is connected to the drain of the internal boost low-side power MOSFET and the source of internal boost high-side power MOSFET.
11VOUTPWROutput of the buck-boost converter.
12ISPIPositive input of the current sense amplifier. An optional current sense resistor connected between the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current limit setting value in the register, a slow constant current control loop becomes active and starts to regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin together with the VOUT pin can disable the output current limit function. It must not be left open.
13ISNINegative input of the current sense amplifier. An optional current sense resistor connected between the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current limit setting value in the register, a slow constant current control loop becomes active and starts to regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin together with the VOUT pin can disable the output current limit function. It must not be left open.
14FB/INTI/OWhen the device is set to use external output voltage feedback, connect to the center tap of a resistor divider to program the output voltage. When the device is set to use internal feedback, this pin is a fault indicator open-drain output. When there is an internal fault happening, this pin outputs logic low level.
15COMPOOutput of the internal error amplifier. Connect the loop compensation network between this pin and the AGND pin.
16CDCOVoltage output proportional to the sensed voltage between the ISP pin and the ISN pin. Use a resistor between this pin and AGND to increase the output voltage to compensate voltage droop across the cable caused by the cable resistance. This pin can be left open if using internal cable voltage droop compensation.
17AGND-Signal ground of the device.
18VCCOOutput of the internal regulator. A ceramic capacitor of more than 4.7μF is required between this pin and the AGND pin.
19BOOT2OPower supply for high-side MOSFET gate driver in boost side. A ceramic capacitor of 0.1µF must be connected between this pin and the SW2 pin.
20BOOT1OPower supply for high-side MOSFET gate driver in buck side. A ceramic capacitor of 0.1µF must be connected between this pin and the SW1 pin.
21EXTVCCISelect the internal LDO or external 5V for VCC. When it is connected to VCC pin, logic high voltage or is left floating, select the internal LDO. When it is connected to logic low voltage, select the external 5V for VCC.