SLVSGT5 December 2023 TPS55289-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
VIN | Input voltage range | 3.0 | 36 | V | ||
VVIN_UVLO | Under voltage lockout threshold | VIN rising | 2.8 | 2.9 | 3.0 | V |
VIN falling | 2.6 | 2.65 | 2.7 | V | ||
IQ | Quiescent current into VIN pin | IC enabled, no load, no switching. VIN = 3.0V to 24V, VOUT = 0.8V, VFB = VREF + 0.1V, RFSW = 100kΩ | 760 | 860 | µA | |
Quiescent current into VOUT pin | IC enabled, no load, no switching. VIN = 3.0V, VOUT = 3V to 20V, VFB = VREF + 0.1V, RFSW = 100kΩ | 760 | 860 | µA | ||
ISD | Shutdown current into VIN pin | IC disabled, VIN = 3.0V to 14V, TJ up to 125°C, EXTVCC pin floating | 0.8 | 3 | µA | |
VCC | Internal regulator output | IVCC = 50mA, VIN = 8V, VOUT = 20V | 5.0 | 5.2 | 5.4 | V |
EN/UVLO | ||||||
VEN_H | EN Logic high threshold | VCC = 3.0V to 5.5V | 1.15 | V | ||
VEN_L | EN Logic low threshold | VCC = 3.0V to 5.5V | 0.4 | V | ||
VEN_HYS | Enable threshold hysteresis | VCC = 3.0V to 5.5V | 0.04 | V | ||
VUVLO | UVLO rising threshold at the EN/UVLO pin | VCC = 3.0V to 5.5V | 1.20 | 1.23 | 1.26 | V |
VUVLO_HYS | UVLO threshold hysteresis | VCC = 3.0V to 5.5V | 10 | mV | ||
IUVLO | Sourcing current at the EN/UVLO pin | VEN/UVLO = 1.3V | 4.4 | 5 | 5.6 | µA |
OUTPUT | ||||||
VOUT | Output voltage range | 0.8 | 22 | V | ||
VOVP | Output overvoltage protection threshold | 22.5 | 23.5 | 24.5 | V | |
VOVP_HYS | Overvoltage protection hysteresis | 1 | V | |||
IFB_LKG | Leakage current at FB pin | TJ up to 125°C | 100 | nA | ||
IVOUT_LKG | Leakage current into VOUT pin | IC disabled, VOUT = 20V, VSW2 = 0V, TJ up to 125°C | 1 | 20 | µA | |
IDISCHG | Output discharge current | VOUT = 20V, VCC = 5.2V | 40 | 100 | 170 | mA |
INTERNAL REFERENCE DAC | ||||||
VOUT_FULL | Output voltage when VREF is set to 1.129V | VOUT_FS = 03h, REF = 0780h, VREF = 1.129V | 19.7 | 20 | 20.3 | V |
VOUT_FS = 02h, REF = 0780h, VREF = 1.129V | 14.78 | 15 | 15.22 | V | ||
VOUT_FS = 01h, REF = 0780h, VREF = 1.129V | 9.85 | 10 | 10.15 | V | ||
VOUT_FS = 00h, REF = 0780h, VREF = 1.129V | 4.93 | 5 | 5.07 | V | ||
VOUT_ZERO | Output voltage when VREF is set to 45mV | VOUT_FS = 03h, REF = 0000h, VREF = 45mV | 0.74 | 0.8 | 0.86 | V |
VOUT_FS = 02h, REF = 0000h, VREF = 45mV | 0.55 | 0.6 | 0.65 | V | ||
VOUT_FS = 01h, REF = 0000h, VREF = 45mV | 0.36 | 0.4 | 0.44 | V | ||
VOUT_FS = 00h, REF = 0000h, VREF = 45mV | 0.18 | 0.2 | 0.22 | V | ||
REFERENCE VOLTAGE | ||||||
VREF | Reference voltage at the FB/INT pin when using external feedback | External feedback with REF = 0780h | 1.117 | 1.129 | 1.141 | V |
External feedback with REF = 058Ch | 0.837 | 0.846 | 0.855 | V | ||
External feedback with REF = 0334h | 0.502 | 0.508 | 0.514 | V | ||
External feedback with REF = 01A4h | 0.276 | 0.282 | 0.288 | V | ||
POWER SWITCH | ||||||
RDS(on) | Low-side MOSFET on resistance at buck side | VOUT = 20V, VCC = 5.2V | 22 | mΩ | ||
High-side MOSFET on resistance at buck side | VOUT = 20V, VCC = 5.2V | 14 | mΩ | |||
Low-side MOSFET on resistance at boost side | VOUT = 20V, VCC = 5.2V | 11 | mΩ | |||
High-side MOSFET on resistance at boost side | VOUT = 20V, VCC = 5.2V | 11 | mΩ | |||
INTERNAL CLOCK | ||||||
fSW | Switching frequency | RFSW = 100k | 180 | 200 | 220 | kHz |
RFSW = 8.4k | 2000 | 2200 | 2400 | kHz | ||
tOFF_min | Minimum off time | Boost mode | 90 | 145 | ns | |
tON_min | Minimum on time | Buck mode | 90 | 130 | ns | |
VSW | Voltage at the FSW pin | 1 | V | |||
CURRENT LIMIT | ||||||
ILIM_AVG | Average inductor current limit | VIN = 8V, VOUT = 20V, FSW = 400kHz | 7 | 8 | 9 | A |
ILIM_PK_H | Peak inductor current limit at boost high side | VIN = 8V, VOUT = 20V, FSW = 400kHz | 13 | A | ||
ILIM_PK_L | Peak inductor current limit at boost low side | VIN = 8V, VOUT = 20V, FSW = 400kHz | 12 | A | ||
VSNS | Current loop regulation voltage between ISP and ISN pin | VISN = 2V to 21V, IOUT_LIMIT Register = 10111100b | 28.5 | 30 | 31.5 | mV |
VISN = 2V to 21V, IOUT_LIMIT Register = 11100100b | 48 | 50 | 52 | mV | ||
CABLE VOLTAGE DROOP COMPENSATION | ||||||
VCDC | Voltage at the CDC pin | RCDC = 20kΩ or floating, VISP – VISN = 50mV | 0.95 | 1 | 1.05 | V |
RCDC = 20kΩ or floating, VISP – VISN = 2mV | 40 | 75 | mV | |||
VOUT_CDC | VOUT increase for cable droop compensation | Internal output feedback, CDC[2:0] = 111, VISP – VISN = 50mV | 640 | 700 | 750 | mV |
Internal output feedback, CDC[2:0] = 111, VISP – VISN = 2mV | 30 | 60 | mV | |||
Internal output feedback, CDC[2:0] = 001, VISP – VISN = 50mV | 70 | 100 | 130 | mV | ||
Internal output feedback, CDC[2:0] = 001, VISP – VISN = 10mV | 20 | 40 | mV | |||
IFB_CDC | FB/INT pin sinking current | External output feedback, RCDC = 20kΩ, VISP – VISN = 50mV | 7.23 | 7.5 | 7.87 | µA |
External output feedback, RCDC = 20kΩ, VISP – VISN = 0mV | 0 | 0.3 | µA | |||
External output feedback, RCDC = floating, VISP – VISN = 50mV | 0 | 0.3 | µA | |||
ERROR AMPLIFIER | ||||||
ISINK | COMP pin sink current | VFB = VREF + 400mV, VCOMP = 1.5V, VCC=5V | 20 | µA | ||
ISOURCE | COMP pin source current | VFB = VREF - 400mV, VCOMP = 1.5V, VCC=5V | 60 | µA | ||
VCCLPH | High clamp voltage at the COMP pin | FPWM mode, VOUT = 1.8V to 22V | 1.3 | V | ||
VCCLPL | Low clamp voltage at the COMP pin | FPWM mode, VOUT = 1.8V to 22V | 0.7 | V | ||
GEA | Error amplifier transconductance | 190 | µA/V | |||
SOFT START | ||||||
tSS | Soft-start time | 2.5 | 3.6 | 5 | ms | |
SPREAD SPECTRUM | ||||||
IDITH_CHG | Dithering charge current | VDITH/SYNC = 1.0V, RFSW = 49.9kΩ, voltage rising from 0.9V | 2 | µA | ||
IDITH_DIS | Dithering discharge current | VDITH/SYNC = 1.0V, RFSW = 49.9kΩ, voltage falling from 1.1V | 2 | µA | ||
VDITH_H | Dithering high threshold | 1.07 | V | |||
VDITH_L | Dithering low threshold | 0.93 | V | |||
SYNCHRONOUS CLOCK | ||||||
VSNYC_H | Sync clock high voltage threshold | 1.2 | V | |||
VSYNC_L | Sync clock low voltage threshold | 0.4 | V | |||
tSYNC_MIN | Minimum sync clock pulse width | 50 | ns | |||
HICCUP | ||||||
tHICCUP | Hiccup off time | 76 | ms | |||
MODE | ||||||
VMODE | MODE logic high threshold | VCC = 3.0V to 5.5V | 1.2 | V | ||
VMODE | MODE logic low threshold | VCC = 3.0V to 5.5V | 0.4 | V | ||
EXTVCC | ||||||
VEXTVCC | EXTVCC Logic high threshold | VCC = 3.0V to 5.5V | 1.2 | V | ||
VEXTVCC | EXTVCC Logic Low threshold | VCC = 3.0V to 5.5V | 0.4 | V | ||
LOGIC INTERFACE | ||||||
VI2C_IO | IO voltage range for I2C | 1.7 | 5.5 | V | ||
VI2C_H | I2C input high threshold | VCC = 3.0V to 5.5V | 1.2 | V | ||
VI2C_L | I2C input low threshold | VCC = 3.0V to 5.5V | 0.4 | V | ||
IFB/INT_H | Leakage current into FB/INT pin when outputting high impedance | VFB/INT = 5V | 100 | nA | ||
VFB/INT_L | Output low voltage range of the FB/INT pin | Sinking 4mA current | 0.03 | 0.1 | V | |
PROTECTION | ||||||
TSD | Thermal shutdown threshold | TJ rising | 175 | °C | ||
TSD_HYS | Thermal shutdown hysteresis | TJ falling below Tsd | 20 | °C |