SLVSCG7A July   2014  – September 2021 TPS55340-EP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Switching Frequency
      2. 8.3.2  Voltage Reference and Setting Output Voltage
      3. 8.3.3  Soft Start
      4. 8.3.4  Slope Compensation
      5. 8.3.5  Overcurrent Protection and Frequency Foldback
      6. 8.3.6  Enable and Thermal Shutdown
      7. 8.3.7  Undervoltage Lockout (UVLO)
      8. 8.3.8  Minimum On-Time and Pulse Skipping
      9. 8.3.9  Layout Considerations
      10. 8.3.10 Thermal Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VIN < 2.9 V (Minimum VIN)
      2. 8.4.2 Synchronization
      3. 8.4.3 Oscillator
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Boost Converter Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Selecting the Switching Frequency (R4)
          2. 9.2.1.2.2  Determining the Duty Cycle
          3. 9.2.1.2.3  Selecting the Inductor (L1)
          4. 9.2.1.2.4  Computing the Maximum Output Current
          5. 9.2.1.2.5  Selecting the Output Capacitor (C8 to C10)
          6. 9.2.1.2.6  Selecting the Input Capacitors (C2, C7)
          7. 9.2.1.2.7  Setting Output Voltage (R1, R2)
          8. 9.2.1.2.8  Setting the Soft-Start Time (C7)
          9. 9.2.1.2.9  Selecting the Schottky Diode (D1)
          10. 9.2.1.2.10 Compensating the Control Loop (R3, C4, C5)
        3. 9.2.1.3 Application Curves
      2. 9.2.2 SEPIC Converter Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1  Selecting the Switching Frequency (R4)
          2. 9.2.2.2.2  Duty Cycle
          3. 9.2.2.2.3  Selecting the Inductor (L1)
          4. 9.2.2.2.4  Calculating the Maximum Output Current
          5. 9.2.2.2.5  Selecting the Output Capacitor (C8 to C10)
          6. 9.2.2.2.6  Selecting the Series Capacitor (C6)
          7. 9.2.2.2.7  Selecting the Input Capacitor (C2, C7)
          8. 9.2.2.2.8  Selecting the Schottky Diode (D1)
          9. 9.2.2.2.9  Setting the Output Voltage (R1, R2)
          10. 9.2.2.2.10 Setting the Soft-Start Time (C3)
          11. 9.2.2.2.11 MOSFET Rating Considerations
          12. 9.2.2.2.12 Compensating the Control Loop (R3, C4)
        3. 9.2.2.3 SEPIC Converter Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.1.2.5 Selecting the Output Capacitor (C8 to C10)

TI recommends at least 4.7 µF of ceramic type X5R or X7R capacitance at the output. The output capacitance is mainly selected to meet the requirements for the output ripple (VRIPPLE) and voltage change during a load transient. Then the loop is compensated for the output capacitor selected. The output capacitance should be chosen based on the most stringent of these criteria. The output ripple voltage is related to the capacitance and equivalent series resistance (ESR) of the output capacitor. Assuming a capacitor with 0 ESR, the minimum capacitance needed for a given ripple can be calculated by Equation 18. If high-ESR capacitors are used, it will contribute additional ripple. The maximum ESR for a specified ripple is calculated with Equation 19. ESR ripple can be neglected for ceramic capacitors, but must be considered if tantalum or electrolytic capacitors are used. The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated by the Equation 20. Equation 21 can be used to calculate the RMS current that the output capacitor needs to support.

Equation 18. GUID-A2322DD3-4B01-4D93-93E5-205A1CC85C6A-low.gif
Equation 19. GUID-ED664AED-2E53-4906-8FE3-3C39B2F556FA-low.gif
Equation 20. GUID-F520918E-3046-450F-9606-35F32D6378C9-low.gif
Equation 21. GUID-820C841E-2182-47B2-929B-C698EE7E29A6-low.gif

Using Equation 18 for this design, the minimum output capacitance for the specified 120-mV output ripple is 8.8 µF. For a maximum transient voltage change (ΔVTRAN) of 960 mV with a 400-mA load transient (ΔITRAN) and a 6-kHz control loop bandwidth (ƒBW) with Equation 20, the minimum output capacitance is 11.1 µF. The most stringent criteria is the 11.1 µF for the required load transient. Equation 21 gives a 1.58-A RMS current in the output capacitor. The capacitor should also be properly rated for the desired output voltage.

Take care when evaluating ceramic capacitors that derate under DC bias, aging, and AC signal conditions. For example, larger form factor capacitors (in 1206 size) have self-resonant frequencies in the range of converter switching frequency. Self-resonance causes the effective capacitance to be significantly lower. The DC bias can also significantly reduce capacitance. Ceramic capacitors can lose as much as 50% of the capacitance when operated at the rated voltage. Therefore, allow margin in selected capacitor voltage rating to ensure adequate capacitance at the required output voltage. For this example, three 4.7-µF, 50-V 1210 X7R ceramic capacitors are used in parallel leading to a negligible ESR. Choosing 50-V capacitors instead of 35 V reduces the effects of DC bias and allows this example circuit to be rated for the maximum output voltage range of the TPS55340-EP.