SLVSCG7A July   2014  – September 2021 TPS55340-EP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Switching Frequency
      2. 8.3.2  Voltage Reference and Setting Output Voltage
      3. 8.3.3  Soft Start
      4. 8.3.4  Slope Compensation
      5. 8.3.5  Overcurrent Protection and Frequency Foldback
      6. 8.3.6  Enable and Thermal Shutdown
      7. 8.3.7  Undervoltage Lockout (UVLO)
      8. 8.3.8  Minimum On-Time and Pulse Skipping
      9. 8.3.9  Layout Considerations
      10. 8.3.10 Thermal Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VIN < 2.9 V (Minimum VIN)
      2. 8.4.2 Synchronization
      3. 8.4.3 Oscillator
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Boost Converter Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Selecting the Switching Frequency (R4)
          2. 9.2.1.2.2  Determining the Duty Cycle
          3. 9.2.1.2.3  Selecting the Inductor (L1)
          4. 9.2.1.2.4  Computing the Maximum Output Current
          5. 9.2.1.2.5  Selecting the Output Capacitor (C8 to C10)
          6. 9.2.1.2.6  Selecting the Input Capacitors (C2, C7)
          7. 9.2.1.2.7  Setting Output Voltage (R1, R2)
          8. 9.2.1.2.8  Setting the Soft-Start Time (C7)
          9. 9.2.1.2.9  Selecting the Schottky Diode (D1)
          10. 9.2.1.2.10 Compensating the Control Loop (R3, C4, C5)
        3. 9.2.1.3 Application Curves
      2. 9.2.2 SEPIC Converter Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1  Selecting the Switching Frequency (R4)
          2. 9.2.2.2.2  Duty Cycle
          3. 9.2.2.2.3  Selecting the Inductor (L1)
          4. 9.2.2.2.4  Calculating the Maximum Output Current
          5. 9.2.2.2.5  Selecting the Output Capacitor (C8 to C10)
          6. 9.2.2.2.6  Selecting the Series Capacitor (C6)
          7. 9.2.2.2.7  Selecting the Input Capacitor (C2, C7)
          8. 9.2.2.2.8  Selecting the Schottky Diode (D1)
          9. 9.2.2.2.9  Setting the Output Voltage (R1, R2)
          10. 9.2.2.2.10 Setting the Soft-Start Time (C3)
          11. 9.2.2.2.11 MOSFET Rating Considerations
          12. 9.2.2.2.12 Compensating the Control Loop (R3, C4)
        3. 9.2.2.3 SEPIC Converter Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.2.2.6 Selecting the Series Capacitor (C6)

The series capacitor is chosen to limit the ripple current to 5% of the maximum input voltage. Using Equation 47, the minimum capacitance is 1.5 µF. Using Equation 48, the RMS current is calculated to be 1.63 A. A 2.2-µF ceramic capacitor in a 1206 package is selected.

Equation 47. GUID-35ACF526-DA14-447F-B883-D68F2F2F3D05-low.gif
Equation 48. GUID-F6DFFA2E-A79F-4126-9014-0E134C5E05DB-low.gif