The TPS55340-Q1 device requires external compensation, which allows the loop response to be optimized for each application. The COMP pin is the output of the internal error amplifier. An external resistor (R3) and ceramic capacitor (C4) are connected to the COMP pin to provide a pole and a zero as shown in the application circuit (see Figure 8-1). This pole and zero, along with the inherent pole and zero of a boost converter, determine the closed loop frequency response, which is important for converter stability and transient response. Loop compensation must be designed for the minimum operating voltage.

The following equations summarize the loop equations for the TPS55340-Q1 device configured as a CCM boost converter. The equations include the power stage output pole (ƒ_O) and the right-half-plane zero (ƒ_(RHPZ)) of a boost converter calculated using Equation 29 and Equation 30, respectively. When calculating ƒ_O, including the derating of ceramic output capacitors is important. In the example with an estimated 10.2-µF capacitance, these frequencies are calculated to be 980 kHz and 22.1 kHz, respectively. Use Equation 29 to calculate the DC gain (A) of the power stage, which is 39.9 dB in this design. Use Equation 32 and Equation 33 to calculate the compensation pole (ƒ_(P)) and zero (ƒ_(Z)) generated by R3, C4, and the internal transconductance amplifier (respectively).

Most CCM boost converters have a stable control loop if ƒ_(Z) is set slightly above ƒ_(P) through proper sizing of R3 and C4. To start, select a value of 0.1 µF for C4 and a value of 2 kΩ for R3. Increasing R3 or reducing C4 increases the closed loop bandwidth, and therefore improves the transient response. Adjusting R3 and C4 in opposite directions increases the phase and gain margin of the loop, which improves loop stability. TI recommends to limit the bandwidth of the loop to the lower of either 1/5 of the switching frequency (ƒ_S) or 1/3 the RHPZ frequency (ƒ_(RHPZ)), which is calculated using Equation 30. Use the spreadsheet tool located on the TPS55340-Q1 product page as an aid in compensation design.

Equation 29.

where

• C_O is the equivalent output capacitor (C_O = C8 + C9 + C10).
• R_O is the equivalent load resistance (V_O / I_O).

Equation 30.

Equation 31.

where

• g_ea is the error amplifier transconductance located in Section 6.5.
• R_(SENSE) (15 mΩ, typical) is the sense resistor in the current control loop.

Equation 32.

Equation 33.

Equation 34.

where

• ƒ_CO(1) is possible bandwidth.

Equation 35.

where

• ƒ_CO(2) is possible bandwidth.

An additional capacitor from the COMP pin to the GND pin (C5) can be used to place a high frequency pole in the control loop. Using this additional capacitor is not always required when using ceramic output capacitors. If a non-ceramic output capacitor is used, an additional zero (ƒ_(ZESR)) is located in the control loop. Use Equation 37 to calculate ƒ_(ZESR). Use Equation 38 and Equation 36 to calculate the value of C5 and the pole created by C5, respectively. Finally, if additional phase margin is required, add an additional zero (f_(ZFF)) by placing a capacitor (C_(FF)) in parallel with the top feedback resistor (R1). TI recommends to place the zero at the target cross-over frequency or higher. The feed forward capacitor also adds a pole at a higher frequency. Use Equation 39 to calculate the recommended value of C_(FF).

Equation 36.

Equation 37.

Equation 38.

where

• R_(ESR) is the ESR of the output capacitor

Equation 39.

If a network measurement tool is available, the most accurate compensation design can be achieved following this procedure. The power stage frequency response is first measured using a network analyzer at the minimum 5-V input and maximum 800-mA load. Figure 8-2 shows this measurement. In this design, only one pole and one zero are used, therefore, the maximum phase increase from the compensation is 180 degrees. For a 60 degree phase margin, the power stage phase must be –120 degrees at the lowest point. Based on the target
6-kHz bandwidth, the measured power stage gain, K_(PS) (ƒ_BW), is 24.84 dB and the phase is –110.3 degrees.

Figure 8-2 Power Stage Gain and Phase of the Boost Converter

The value of R3 is then selected to set the compensation gain as the reciprocal of the power stage gain at the target bandwidth using Equation 40. The value of C4 is then selected to place a zero at 1/10 the target bandwidth using Equation 41. In this case, R3 is calculated to be 2.56 kΩ, and the nearest standard value 2.55 kΩ is used. The value of C4 is calculated to be 0.104 µF and the nearest standard value of 0.100 µF is used. A 100-pF capacitor is selected for C5 to add a high frequency pole at a frequency 100 times the target bandwidth, however adding 100 pF for C5 is not necessary because this design uses all ceramic capacitors.

Equation 40.

Equation 41.