SLVSBV5C June   2014  – September 2021 TPS55340-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operation
      2. 7.3.2 Switching Frequency
      3. 7.3.3 Overcurrent Protection and Frequency Foldback
        1. 7.3.3.1 Minimum On Time and Pulse Skipping
      4. 7.3.4 Voltage Reference and Setting Output Voltage
      5. 7.3.5 Soft Start
      6. 7.3.6 Slope Compensation
      7. 7.3.7 Enable and Thermal Shutdown
      8. 7.3.8 Undervoltage Lockout (UVLO)
      9. 7.3.9 Thermal Considerations
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VI < 2.9 V (Minimum VI)
      2. 7.4.2 Operation With EN Control
      3. 7.4.3 Operation at Light Loads
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS55340-Q1 Boost Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Selecting the Switching Frequency (R4)
          3. 8.2.1.2.3  Determining the Duty Cycle
          4. 8.2.1.2.4  Selecting the Inductor (L1)
          5. 8.2.1.2.5  Computing the Maximum Output Current
          6. 8.2.1.2.6  Selecting the Output Capacitor (C8 through C10)
          7. 8.2.1.2.7  Selecting the Input Capacitors (C2 and C7)
          8. 8.2.1.2.8  Setting the Output Voltage (R1 and R2)
          9. 8.2.1.2.9  Setting the Soft-Start Time (C7)
          10. 8.2.1.2.10 Selecting the Schottky Diode (D1)
          11. 8.2.1.2.11 Compensating the Control Loop (R3, C4, and C5)
        3. 8.2.1.3 Application Curves
      2. 8.2.2 TPS55340-Q1 SEPIC Converter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Selecting the Switching Frequency (R4)
          2. 8.2.2.2.2  Duty Cycle
          3. 8.2.2.2.3  Selecting the Inductor (L1)
          4. 8.2.2.2.4  Calculating the Maximum Output Current
          5. 8.2.2.2.5  Selecting the Output Capacitor (C8 Through C10)
          6. 8.2.2.2.6  Selecting the Series Capacitor (C6)
          7. 8.2.2.2.7  Selecting the Input Capacitor (C2 and C7)
          8. 8.2.2.2.8  Selecting the Schottky Diode (D1)
          9. 8.2.2.2.9  Setting the Output Voltage (R1 and R2)
          10. 8.2.2.2.10 Setting the Soft-Start Time (C3)
          11. 8.2.2.2.11 Mosfet Rating Considerations
          12. 8.2.2.2.12 Compensating the Control Loop (R3 and C4)
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.2.1.2.6 Selecting the Output Capacitor (C8 through C10)

At least 4.7 µF of ceramic type X5R or X7R capacitance is recommended at the output. This output capacitance was selected to meet the requirements for the output ripple (Vrip) and voltage change during a load transient. The loop is then compensated for the selected output capacitor. The output capacitance must be selected based on the most stringent of these criteria. The output ripple voltage is related to the capacitance and equivalent series resistance (ESR) of the output capacitor. Assuming a capacitor with zero ESR, use Equation 20 to calculate the minimum capacitance required for a given ripple. Using high-ESR capacitors causes additional ripple. Use Equation 21 to calculate the maximum ESR for a specified ripple. ESR ripple can be neglected for ceramic capacitors, but must be considered if tantalum or electrolytic capacitors are used. Use Equation 22 to calculate the minimum ceramic output capacitance required to meet a load transient requirement. Use Equation 23 to calculate the RMS current required by the output capacitor for support.

Equation 20. GUID-7A2FF545-9A80-4252-9FDC-978DF5DD799F-low.gif
Equation 21. GUID-F2C51A67-86C5-4481-B77B-618052AA5A91-low.gif
Equation 22. GUID-596DE4DD-9B98-4426-BCF3-D3B931AE865E-low.gif
Equation 23. GUID-81B5A081-DC7A-453C-B518-6A52BFCB1FE2-low.gif

Using Equation 20 for this design, the minimum output capacitance for the specified 120-mV output ripple is 8.8 µF. For a maximum transient voltage change (ΔV(TRAN)) of 960 mV with a 400-mA load transient (ΔI(TRAN)), and a 6-kHz control loop bandwidth (ƒBW) with Equation 22, the minimum output capacitance is calculated as 11.1 µF. The most stringent criterion is the 11.1 µF for the required load transient. Equation 23 calculates a 1.58-A RMS current in the output capacitor. The capacitor must also be properly rated for the desired output voltage.

Care must be taken when evaluating ceramic capacitors that derate under DC bias, aging, and AC signal conditions. For example, larger form factor capacitors (in 1206 size) have self-resonant frequencies in the range of the converter switching frequency. Self resonance significantly decreases the effective capacitance. The DC bias also significantly reduces capacitance. Ceramic capacitors can lose as much as 50% of the capacitance when operated at the rated voltage. Therefore, leave a margin when selecting the capacitor voltage rating to ensure adequate capacitance at the required output voltage. For this example, three 4.7-µF, 50-V 1210 X7R ceramic capacitors are used in parallel, leading to a negligible ESR. Selecting 50-V capacitors instead of 35-V capacitors reduces the effects of DC bias and allows this example circuit to be rated for the maximum output voltage range of the TPS55340-Q1 device.