SLUSDF5A January   2019  – August 2019 TPS560430-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Output Current VOUT = 5 V, 2100 kHz, PFM
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fixed Frequency Peak Current Mode Control
      2. 8.3.2 Adjustable Output Voltage
      3. 8.3.3 Enable
      4. 8.3.4 Minimum ON-Time, Minimum OFF-Time and Frequency Foldback
      5. 8.3.5 Bootstrap Voltage
      6. 8.3.6 Over Current and Short Circuit Protection
      7. 8.3.7 Soft Start
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 CCM Mode
      4. 8.4.4 Light-Load Operation (PFM Version)
      5. 8.4.5 Light-Load Operation (FPWM Version)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Output Voltage Set-Point
        3. 9.2.2.3 Switching Frequency
        4. 9.2.2.4 Inductor Selection
        5. 9.2.2.5 Output Capacitor Selection
        6. 9.2.2.6 Input Capacitor Selection
        7. 9.2.2.7 Bootstrap Capacitor
        8. 9.2.2.8 Under Voltage Lockout Set-Point
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Compact Layout for EMI Reduction
      2. 11.1.2 Feedback Resistors
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25 °C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 4 V to 36 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN Operation input voltage 4 36 V
VIN_UVLO Undervoltage lockout thresholds Rising threshold 3.55 3.75 4.00 V
Falling threshold 3.25 3.45 3.65
Hysteresis 0.3
IQ Operating quiescent current (non-switching) PFM version, VEN = 3.3 V, VFB = 1.1V 80 120 µA
ISHDN Shutdown current VEN = 0 V 3 10 µA
ENABLE (EN PIN)
VEN_H Enable rising threshold voltage 1.1 1.23 1.36 V
VEN_L Enable falling threshold voltage 0.95 1.1 1.22 V
VEN_HYS Enable hysteresis voltage 0.13 V
IEN Leakage current at EN pin VEN = 3.3 V 10 200 nA
VOLTAGE REFERENCE (FB PIN)
VREF Reference voltage TJ = 25 °C 0.995 1.00 1.005 V
TJ = –40 °C to 125 °C 0.985 1.00 1.015 V
IFB Leakage current at FB pin VFB = 1.2 V 0.2 50 nA
CURRENT LIMITS AND HICCUP
IHS_LIMIT Peak inductor current limit 0.8 1.1 1.4 A
ILS_LIMIT Valley inductor current limit 0.62 0.8 0.98 A
ILS_ZC Zero cross current (PFM version) 20 mA
ILS_NEG Negative current limit (FPWM version) -0.7 -0.5 -0.3 A
VHICCUP Hiccup threshold of FB pin % of reference voltage 40%
INTEGRATED MOSFETS
RDS_ON_HS High-side MOSFET ON-resistance TJ = 25 °C, VIN = 12 V 450 mΩ
RDS_ON_LS Low-side MOSFET ON-resistance TJ = 25 °C, VIN = 12 V 240 mΩ
THERMAL SHUTDOWN(1)
TSHDN Thermal shutdown threshold 170 °C
THYS Hysteresis 12 °C
(1) Ensured by design.