SLVSE22B September   2017  – June 2018 TPS560430

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Output Current VOUT = 5 V, 1100 kHz, PFM
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fixed Frequency Peak Current Mode Control
      2. 8.3.2 Adjustable Output Voltage
      3. 8.3.3 Enable
      4. 8.3.4 Minimum ON-Time, Minimum OFF-Time and Frequency Foldback
      5. 8.3.5 Bootstrap Voltage
      6. 8.3.6 Over Current and Short Circuit Protection
      7. 8.3.7 Soft Start
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 CCM Mode
      4. 8.4.4 Light-Load Operation (PFM Version)
      5. 8.4.5 Light-Load Operation (FPWM Version)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Output Voltage Set-Point
        3. 9.2.2.3 Switching Frequency
        4. 9.2.2.4 Inductor Selection
        5. 9.2.2.5 Output Capacitor Selection
        6. 9.2.2.6 Input Capacitor Selection
        7. 9.2.2.7 Bootstrap Capacitor
        8. 9.2.2.8 Under Voltage Lockout Set-Point
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Compact Layout for EMI Reduction
      2. 11.1.2 Feedback Resistors
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Fixed Frequency Peak Current Mode Control

The following operation description of the TPS560430 will refer to the Functional Block Diagram and to the waveforms in Figure 13. TPS560430 is a step-down synchronous buck regulator with integrated high-side (HS) and low-side (LS) switches (synchronous rectifier). The TPS560430 supplies a regulated output voltage by turning on the HS and LS NMOS switches with controlled duty cycle. During high-side switch ON time, the SW pin voltage swings up to approximately VIN, and the inductor current iL increase with linear slope (VIN – VOUT) / L. When the HS switch is turned off by the control logic, the LS switch is turned on after an anti-shoot-through dead time. Inductor current discharges through the low-side switch with a slope of –VOUT / L. The control parameter of a buck converter is defined as Duty Cycle D = tON / TSW, where tON is the high-side switch ON time and TSW is the switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an idea Buck converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN.

TPS560430 ccm-slvse22.gifFigure 13. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

The TPS560430 employs fixed-frequency peak-current mode control. A voltage feedback loop is used to get accurate DC voltage regulation by adjusting the peak-current command based on voltage offset. The peak inductor current is sensed from the high-side switch and compared to the peak current threshold to control the ON time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer external components, makes it easy to design, and provides stable operation with almost any combination of output capacitors. The regulator operates with fixed switching frequency at normal load condition. At light-load condition, the TPS560430 operates in PFM mode to maintain high efficiency (PFM version) or in FPWM mode for low output voltage ripple, tight output voltage regulation, and constant switching frequency (FPWM version).