SLUSFG9A April   2024  – June 2024 TPS561243 , TPS561246

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Adaptive On-Time Control and PWM Operation
      2. 6.3.2 Eco-mode Control
      3. 6.3.3 Soft Start and Prebiased Soft Start
      4. 6.3.4 Large Duty Operation
      5. 6.3.5 Current Protection
      6. 6.3.6 Enable Circuit
      7. 6.3.7 Undervoltage Lockout (UVLO) Protection
      8. 6.3.8 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Eco-mode Operation
      2. 6.4.2 FCCM Mode Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 Output Voltage Resistors Selection
        3. 7.2.2.3 Output Filter Selection
        4. 7.2.2.4 Input Capacitor Selection
        5. 7.2.2.5 Bootstrap Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.3 Output Filter Selection

The LC filter used as the output filter has a double pole at Equation 4. In this equation, COUT must use effective value after derating, not nominal value.

Equation 4. Frequencydoublepole=12×π×LOUT×COUT

For any control topology that is compensated internally, there is a range of the output filter that the control topology can support. At low frequency, the overall loop gain is set by the output set point resistor divider network and the internal gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off with a rate of –40dB per decade and the phase has a 180 degree drop. The internal ripple generation network introduces a high-frequency zero that reduces the gain roll off from –40dB to –20dB per decade and leads to the 90 degree phase boost. The high frequency zero brought by the internal ripple injection circuit is about 160kHz. TI recommends the double pole frequency brought by the selected inductor and capacitor to be located at about 40kHz, so that the phase boost provided by this high frequency zero provides adequate phase margin for the stability requirement. For output voltage higher than 2V, TI suggests to add a CFF capacitor to increase the bandwidth and the phase margin. The CFF range suggested is from 10pF to 100pF. The crossover frequency of the overall system must usually be targeted to be less than one-third of the switching frequency.

Table 7-2 Recommended Component Values
OUTPUT VOLTAGE (V) LOUT (uH) COUT(uF) COUT(uF) (1) Range RFBT (kΩ) RFBB (kΩ) CFF(pF)
0.6 1 22 (10V Rated) 20-90 0 10.0 -
1.05 1.2 22 (10V Rated) 10-45 7.5 10.0 -
3.3 3.3 22 (25V Rated) 15-60 135.0 30.0 47
5 3.3 22 (25V Rated) 15-60 220.0 30.0 47
7 3.3 22x2 (25V Rated) 15-60 320.0 30.0 47
(1) A ceramic capacitor is used in this table. All the COUT values are after derating.

The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5, Equation 6, and Equation 7. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current.

Equation 5. IP-P=VOUTVINMax×VINMax-VOUTLOUT×fSW
Equation 6. IPEAK=IO+IP-P2
Equation 7. ILO(RMS)=IO2+112×IP-P2

For this design example, the calculated peak current is 1.32A and the calculated RMS current is 1.02A. The inductor used is WE 74438357012.

The capacitor value and ESR determines the amount of output voltage ripple. The TPS56124x is intended for use with ceramic or other low ESR capacitors. TI recommends to use 1× 22µF output cap. Use Equation 8 to determine the required RMS current rating for the output capacitor.

Equation 8. ICO(RMS)=VOUT×VIN-VOUT12×VIN×LOUT×fSW

For this design, one MuRata GRM21BR61A226ME44L 22µF output capacitor can be used. The typical ESR is 2mΩ each. The calculated RMS current is 0.2A and each output capacitor is rated for 4A.