SLUSFG9A April   2024  – June 2024 TPS561243 , TPS561246

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Adaptive On-Time Control and PWM Operation
      2. 6.3.2 Eco-mode Control
      3. 6.3.3 Soft Start and Prebiased Soft Start
      4. 6.3.4 Large Duty Operation
      5. 6.3.5 Current Protection
      6. 6.3.6 Enable Circuit
      7. 6.3.7 Undervoltage Lockout (UVLO) Protection
      8. 6.3.8 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Eco-mode Operation
      2. 6.4.2 FCCM Mode Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 Output Voltage Resistors Selection
        3. 7.2.2.3 Output Filter Selection
        4. 7.2.2.4 Input Capacitor Selection
        5. 7.2.2.5 Bootstrap Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Layout Guidelines

  1. Make VIN and GND traces as wide as possible to reduce trace impedance. The wide areas can also benefit for heat dissipation.
  2. Place the input capacitor and output capacitor as close to the device as possible to minimize trace impedance.
  3. Provide sufficient vias for the input capacitor and output capacitor.
  4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
  5. Do not allow switching current to flow under the device.
  6. Connect a separate VOUT path to the upper feedback resistor.
  7. Make a Kelvin connection to the GND pin for the feedback path.
  8. Place a voltage feedback loop away from the high voltage switching trace, and preferably with ground shield.
  9. Make the trace of the FB node as small as possible to avoid noise coupling.
  10. Make the GND trace between the output capacitor and the GND pin as wide as possible to minimize trace impedance.