SLUSFG9A April   2024  – June 2024 TPS561243 , TPS561246

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Adaptive On-Time Control and PWM Operation
      2. 6.3.2 Eco-mode Control
      3. 6.3.3 Soft Start and Prebiased Soft Start
      4. 6.3.4 Large Duty Operation
      5. 6.3.5 Current Protection
      6. 6.3.6 Enable Circuit
      7. 6.3.7 Undervoltage Lockout (UVLO) Protection
      8. 6.3.8 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Eco-mode Operation
      2. 6.4.2 FCCM Mode Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 Output Voltage Resistors Selection
        3. 7.2.2.3 Output Filter Selection
        4. 7.2.2.4 Input Capacitor Selection
        5. 7.2.2.5 Bootstrap Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.5 Current Protection

The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored during the OFF state by measuring the low side FET drain to source voltage. This voltage is proportional to the switch current. To improve the accuracy, the voltage sensing is temperature compensated.

During the on time of the high side FET switch, the switch current increases with a linear rate determined by VIN, VOUT, the on-time and the output inductor value. During the on time of the low side FET switch, this current decreases linearly. The average value of the switch current is the load current Iout. If the monitored current is above the OCL level, the converter maintains low side FET on and delays the creation of a new set pulse, even the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.

There are some important considerations for this type of overcurrent protection. The load current is higher than the overcurrent threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being limited, the output voltage tends to fall as the demanded load current can be higher than the current available from the converter. This event can even cause the output voltage to fall. When the FB voltage falls below the UVP threshold voltage, the UVP comparator detects the fall. Then, the device shuts down after the UVP delay time and re-starts after the hiccup time.

When the overcurrent condition is removed, the output voltage returns to the regulated value.

The TPS561246 is an FCCM mode part. In this mode, the device has negative inductor current at light load. The device has NOC (negative overcurrent) protection to avoid too large negative current. NOC protection detects the valley of inductor current. When the valley value of inductor current exceeds the NOC threshold, the IC turns off the low side then turns on the high side. When NOC protection is triggered eight times continuously, IC turns off both high side FET and low side FET. When the NOC condition is removed and output voltage returns to the target value, the device returns to normal switching.

Because the TPS561246 is an FCCM mode part, if the inductance is so small that the device triggers NOC, the output voltage becomes higher than the target value. The minimum inductance is identified as Equation 2.

Equation 2. L=Vout×1-VoutVin2×Frequency×NOCmin