SLUSED9 October   2020 TPS563207S

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Adaptive On-Time Control and PWM Operation
      2. 8.3.2 Soft Start and Pre-Biased Soft Start
      3. 8.3.3 Current Protection
      4. 8.3.4 Undervoltage Lockout (UVLO) Protection
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Standby Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Resistors Selection
        2. 9.2.2.2 Output Filter Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Bootstrap Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-B7442512-E527-4AE8-8992-4572AC703C6F-low.gifFigure 6-1 6-Pin SOT563 DRL Package (Top View)
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
VIN 1 I Input voltage supply pin
SW 2 O Switch node connection between high-side NFET and low-side NFET
GND 3 — Ground pin Source terminal of low-side power NFET as well as the ground terminal for controller circuit. Connect sensitive FB to this GND at a single point.
BST 4 O Supply input for the high-side NFET gate drive circuit. Connect 0.1-µF capacitor between BST and SW pin.
EN 5 I Enable input control. Active high and must be pulled up to enable the device.
FB 6 I Converter feedback input. Connect to output voltage with feedback resistor divider.